N25Q128 Datasheet, PDF (96/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q128 - 1.8 V
Once a bit of the OTP memory has been programmed to '0', it can no longer be set to '1'.
Therefore, as soon as bit 0 of byte 64 (control byte) is set to '0', the 64 bytes of the OTP
memory array become read-only in a permanent way.
Any Program OTP (POTP) instruction issued while an Erase, Program or Write cycle is in
progress is rejected without having any effect on the cycle that is in progress.
Figure 25. Program OTP instruction sequence
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-bit address
Data byte 1
DQ0
S
C
23 22 21
MSB
321076543210
MSB
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data byte 2
Data byte 3
Data byte n
DQ0
7654321076543210
MSB
MSB
76543210
MSB
AI13575
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