N25Q128 Datasheet, PDF (9/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q128 - 1.8 V
List of figures
List of figures
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Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
VDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SO16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
BGA connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Extended SPI protocol example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Non Volatile and Volatile configuration Register Scheme . . . . . . . . . . . . . . . . . . . . . . . . . 33
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Read identification instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Read Data Bytes instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Read Data Bytes at Higher Speed instruction and data-out sequence . . . . . . . . . . . . . . . 82
Dual Output Fast Read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Dual I/O Fast Read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Quad Input/Output Fast Read instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Quad Input/ Output Fast Read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Read OTP instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Write Enable instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Write Disable instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Page Program instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Dual Input Fast Program instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Dual Input Extended Fast Program instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . 93
Quad Input Fast Program instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Quad Input Extended Fast Program instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . 95
Program OTP instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
How to permanently lock the OTP bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Subsector Erase instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Sector Erase instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Bulk Erase instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Read Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Write Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Read Lock Register instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Write to Lock Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Read Flag Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Clear Flag Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Read NV Configuration Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Write NV Configuration Register instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Read Volatile Configuration Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . 109
Write Volatile Configuration Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . 110
Read Volatile Enhanced Configuration Register instruction sequence. . . . . . . . . . . . . . . 110
Write Volatile Enhanced Configuration Register instruction sequence. . . . . . . . . . . . . . . 111
Deep Power-down instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Release from Deep Power-down instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Multiple I/O Read Identification instruction and data-out sequence DIO-SPI . . . . . . . . . . 115
Dual Command Fast Read instruction and data-out sequence DIO-SPI . . . . . . . . . . . . . 116
Read OTP instruction and data-out sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Write Enable instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Write Disable instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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