N25Q128 Datasheet, PDF (142/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q128 - 1.8 V
Figure 82. Program OTP instruction sequence QIO-SPI
S
C
DQ0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Instruction 24-Bit Address
Data Data Data
byte1 byte 2 byte n
20 16 12 8 4 0 4 0 4 0 4 0
DQ1
21 17 13 9 5 1 5 1 5 1 5 1
DQ2
22 18 14 10 6 2 6 2 6 2 6 2
DQ3
23 19 15 11 7 3 7 3 7 3 7 3
9.3.8
Quad_Program_OTP
Subsector Erase (SSE)
For devices with a dedicated part number, at the bottom (or top) of the addressable area
there are 8 boot sectors, each one having 16 4Kbytes subsectors. (See Section 16:
Ordering information.) The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside
the chosen subsector. Before it can be accepted, a Write Enable (WREN) instruction must
previously have been executed.
Apart form the parallelizing of the instruction code and the address on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Subsector Erase
(SSE) instruction of the Extended SPI protocol, please refer to Section 9.1.17: Subsector
Erase (SSE) for further details.
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