N25Q128 Datasheet, PDF (160/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q128 - 1.8 V
9.3.26
Release from Deep Power-down (RDP)
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down (RDP) instruction. Executing this instruction
takes the device out of the Deep Power-down mode. Apart form the parallelizing of the
instruction code on the two pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is
exactly the same as the Release from Deep-Power-down (RDP) instruction of the Extended
SPI protocol. The instruction sequence is shown in Figure 101.
Figure 101. Deep Power-down instruction sequence
S
C
DQ0
DQ1
DQ2
DQ3
01
Instruction
t_RDP
High Impedance
Deep power-down mode Standby mode
Quad_RDP
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