N25Q128 Datasheet, PDF (168/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Power-up and power-down
Figure 105. Power-up timing, Fast POR selected
N25Q128 - 1.8 V
Vcc
V_CC(max)
Chip selection not allowed
WREN issued
V_CC(min)
Chip
reset
V_WI
t_VTR
Polling allowed
SPI protocol
WIP = 1
WEL = 0
t_DTW
All read, WRCR, Polling
WRECR allowed allowed
Device fully accessible
Starting protocol defined by NVCR
WIP = 0
WEL = 0
WIP = 1
WEL = 1
WIP = 0
WEL = 1
time
Figure 106. Power-up timing, Fast POR not selected
Vcc
V_CC(max)
Chip selection not allowed
V_CC(min)
Chip
reset
V_WI
t_VTW = t_VTR + t_DTW
Polling allowed
SPI protocol
WIP = 1
WEL = 0
Device fully accessible
Starting protocol defined by NVCR
WIP = 0
WEL = 0
time
Table 27. Power-up timing and V_WI threshold
Symbol
Parameter
t_VTR(1)
t_DTW(1)
t_VTW(1)
V_WI(1)
V_CC(min) to Read when Fast POR is selected
Time delay to write instruction when Fast POR is selected
V_CC(min) to device fully accessible
Write inhibit voltage
1. These parameters are characterized only.
Min Max Unit
100 µs
500 µs
600 µs
1.5
2.5
V
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