N25Q128 Datasheet, PDF (134/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q128 - 1.8 V
Table 24. Instruction set: QIO-SPI protocol (page 2 of 2)
Instruction
Description
One-byte
Instruction
Code (BIN)
One-byte
Instruction
Code
(HEX)
Address
bytes
Dummy
clock
cycle
Data
bytes
WRNVCR Write NV Configuration Register
1011 0001 B1h
0
0
2
RDVCR
Read Volatile Configuration Register 1000 0101 85h
0
0
1 to ∞
WRVCR
Write Volatile Configuration Register 1000 0001 81h
0
0
1
RDVECR
Read Volatile Enhanced
Configuration Register
0110 0101 65h
0
0
1 to ∞
WRVECR
Write Volatile Enhanced
Configuration Register
0110 0001 61h
0
0
1
DP
Deep Power-down
1011 1001 B9h
0
0
0
RDP
Release from Deep Power-down 1010 1011 ABh
0
0
0
9.3.1
1) The number of Dummy Clock cycles is configurable by the user.
2) SSE is only available in devices with Bottom or Top architecture
Multiple I/O Read Identification (MIORDID)
The Multiple Input/Output Read Identification (MIORDID) instruction allows to read the
device identification data in the QIO-SPI protocol:
„ Manufacturer identification (1 byte)
„ Device identification (2 bytes)
Unlike the RDID instruction of the Extended SPI protocol, the Multiple Input/Output
instruction can not read the Unique ID code (UID) (17 bytes).
For further details on the manufacturer and device identification codes, see 9.1.1: Read
Identification (RDID).
Any Multiple Input/Output Read Identification (MIORDID) instruction while an Erase or
Program cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in parallel on the 4 pins DQ0, DQ1, DQ2 and DQ3. After this, the
24-bit device identification, stored in the memory, will be shifted out on again in parallel on
DQ0, DQ1, DQ2 and DQ3. The identification bits are shifted out 4 at a time during the falling
edge of Serial Clock (C).
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Multiple I/O Read Identification (MIORDID) instruction sequence and data-out sequence
QIO-SPI.
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