N25Q128 Datasheet, PDF (42/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Volatile and Non Volatile Registers
N25Q128 - 1.8 V
Table 7. Volatile Enhanced Configuration Register
Bit
Parameter
Value
Description
0
VECR<7> Quad Input Command
1
0
VECR<6> Dual Input Command
1
Enabled
Disabled (default)
Enabled
Disabled (default)
VECR<5> Reserved
x
Reserved
VECR<4> Reset/Hold disable
0
Disabled
1
Enabled (default)
VECR<3>
Accelerator pin enable in 0
QIO-SPI protocol or in
QIFP/QIEFP
1
Enabled
Disabled (default)
000 reserved
001 90
010 60
VECR<2:0> Output Driver Strength
011 45
100 reserved
101 20
110 15
111 30 (default)
Note
Enable command on four input lines
Enable command on two input lines
Fixed value = 0b
Disable Pad Hold/Reset functionality
The bit must be considered in case of
QIFP, QIEFP, or QIO-SPI protocol. It is
“Don’t Care” otherwise.
Impedance at V_CC/2
6.4.1
Quad Input Command VECR<7>
The Quad Input Command configuration bit can be used to make the memory start working
in QIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register
(WRVECR) instruction. The default value of this bit is 1, corresponding to Extended SPI
protocol, If this bit is set to 0 the memory works in QIO-SPI protocol. If VECR bit 7 is set
back to 1 the memory start working again in Extended SPI protocol, unless the bit 6 is set to
0 (in this case the memory start working in DIO-SPI mode).
Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 7and bit 6 of the
VECR set to 0), the memory will work in QIO-SPI.
6.4.2
Dual Input Command VECR<6>
The Dual Input Command configuration bit can be used to make the memory start working
in DIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register
(WVECR) instruction. The default value of this bit is 1, corresponding to Extended SPI
protocol, if this bit is set to 0 the memory works in DIO-SPI protocol (unless the Volatile
Enhanced Configuration Register bit 7 is also set to 0). If the Volatile Enhanced
Configuration Register bit 6 is set back to 1 the memory start working again in Extended SPI
protocol.
Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 7 and bit 6 of the
VECR are set to 0), the memory will work in QIO-SPI.
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