N25Q128 Datasheet, PDF (141/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q128 - 1.8 V
Instructions
Figure 81. Quad Command Page Program instruction sequence QIO-SPI, 32h
S
Mode 3
C _{Mode 0}
DQ0
515 517 519
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 514 516 518
24-bit address
20 16 12 8 4 0
1
40
Data In
2
3
4040
4
40
Data In
254 255
4040
256
40
DQ1
21 17 13 9 5 1 5 1 5 1 5 1 5 1
515151
DQ2
22 18 14 10 6 2 6 2 6 2 6 2 6 2
6 262 62
DQ3
9.3.7
23 19 15 11 7 3 7 3 7 3 7 3 7 3
MSB MSB MSB
7373 73
MSB MSB MSB
Quad_Command_Page_Program_12h
Program OTP instruction (POTP)
The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP
memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed.
Apart form the parallelizing of the instruction code, address and input data on the four pins
DQ0, DQ1, DQ2 and DQ3, the instruction functionality (as well as the locking OTP method)
is exactly the same as the Program OTP (POTP) instruction of the Extended SPI protocol,
please refer to Section 9.1.16: Program OTP instruction (POTP) for further details.
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