N25Q128 Datasheet, PDF (127/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q128 - 1.8 V
Instructions
9.2.18
Clear Flag Status Register
The Clear Flag Status Register (CLFSR) instruction reset the error Flag Status Register bits
(Erase Error bit, Program Error bit, VPP Error bit, Protection Error bit). It is not necessary to
set the WEL bit before the Clear Flag Status Register instruction is executed. The WEL bit
will be unchanged after this command is executed.
Figure 63. Clear Flag Status Register instruction sequence DIO-SPI
S
0123
C
Instruction
DQ0
DQ1
Dual_Clear_Flag_SR
9.2.19
Read NV Configuration Register
The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile
Configuration Register to be read.
Figure 64. Read NV Configuration Register instruction sequence DIO-SPI
S
0 1 2 3 4 5 6 7 8 9 10 11
C
Instruction
NVCR Out
Byte
Byte
DQ0
6 4 2 0 14 12 10 8
DQ1
7 5 3 1 15 13 11 9
LS Byte
MS Byte
Dual_Read_NVCR
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