N25Q128 Datasheet, PDF (157/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q128 - 1.8 V
Instructions
Figure 98. Read Volatile Enhanced Configuration Register instruction sequence
QIO-SPI
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
Instruction
Volatile Enhanced
Configuration Register Out
DQ0
4040 4040404040
DQ1
5151 5151515151
DQ2
6262 626 2626262
DQ3
7 3 7 3 7 37 3 7 3 7 3 7 3
9.3.24
Quad_Read_VECR
Write Volatile Enhanced Configuration Register
The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new
values to be written to the Volatile Enhanced Configuration register. Before it can be
accepted, a write enable (WREN) instruction must previously have been executed. In case
of Fast POR the WREN instruction is not required because a WREN instruction gets the
device out from the Fast POR state (See Section 11.1: Fast POR).
Apart form the parallelizing of the instruction code and the input data on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Write Volatile
Enhanced Configuration Register (WRVECR) instruction of the Extended SPI protocol,
please refer to Section 9.1.33: Write Volatile Enhanced Configuration Register for further
details.
157/185