N25Q128 Datasheet, PDF (110/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q128 - 1.8 V
Figure 39. Write Volatile Configuration Register instruction sequence
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
Instruction
Volatile Configuration
Register In
DQ0
76543210
High Impedance
MSB
DQ1
Write_VCR
9.1.32
Read Volatile Enhanced Configuration Register
The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the
Volatile Configuration Register to be read.
Figure 40. Read Volatile Enhanced Configuration Register instruction sequence
S
C
DQ0
DQ1
9.1.33
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
High Impedance
Volatile Enhanced
Configuration Register Out
Volatile Enhanced
Configuration Register Out
76543210765432107
MSB
MSB
Read_VECR
Write Volatile Enhanced Configuration Register
The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new
values to be written to the Volatile Enhanced Configuration register. Before it can be
accepted, a write enable (WREN) instruction must previously have been executed. After the
write enable (WREN) instruction has been decoded and executed, the device sets the write
enable latch (WEL). In case of Fast POR, the WREN instruction is not required because a
WREN instruction gets the device out from the Fast POR state (see Section 11.1: Fast
POR).
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