N25Q128 Datasheet, PDF (169/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q128 - 1.8 V
Power-up and power-down
11.1
Fast POR
The Fast POR feature is available to speed up the power-on sequence for applications that
only require reading the memory after the power on sequence (no modify instructions).
If enabled, the Fast POR allows read operations and Volatile Configuration Register and
Volatile Enhanced Configuration Register modifications after less than 100us, providing a
substantially faster application boot phase.
In any case, even if the Fast POR sequence is selected, it is still possible to execute a
modify instruction (erase or program) issuing a WREN instruction. In this case the device
will have a latency time (~500us) after the first WREN instruction to complete POR
sequence. During this latency time, when the power on second phase is running, no
instruction will be accepted except for the polling instruction. During the power on second
phase, both WEL & WIP bits are set to 1. At the end of POR sequence only the WEL bit is
still set to 1.
To select or deselect the Fast POR feature, a Write non Volatile Configuration Register
(WRNVCR) instruction is needed to properly set the dedicated bit (bit 5) of the Non Volatile
Configuration Register.
11.2
Rescue sequence in case of power loss during WRNVCR
If a power loss occurs during a Write Non Volatile Configuration Register instruction, after
the next power on the device could eventually wake up in a not determined state, for
example a not required protocol or XIP mode. In that case a particular rescue sequence
must be used to recover the device at a fixed state (Extended SPI protocol without XIP) until
the next power up. Then to fix the problem definitively is recommended to run the Write Non
Volatile configuration Register again.
The rescue sequence is composed of two parts that have to be run in the correct order.
During all the sequence the TSHSL must be 50ns at least. The sequence is:
DQ0 (PAD DATA) equal to '1' for:
7 clock cycles within S low (S becomes high before 8th clock cycle)
+ 13 clock cycles within S low S becomes high before 14th clock cycle)
+ 25 clock cycles within S low (S becomes high before 26th clock cycle)
To exit from XIP.
DQ0 (PAD DATA) and DQ3 (PAD HOLD) equal to '1' for:
8 clock cycles within S low (S becomes high before 9th clock cycle) to force Normal SPI
protocol.
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