N25Q128 Datasheet, PDF (135/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q128 - 1.8 V
Instructions
Figure 72. Multiple I/O Read Identification instruction and data-out sequence QIO-
SPI
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
AFh ^{MAN. DEV. SIZE}
code code code
DQ0
4040 40
DQ1
5151 51
DQ2
6262 62
DQ3
7373 73
9.3.2
Quad_Multi_Read_IO
Quad Command Fast Read (QCFR)
The Quad Command Fast Read (QCFR) instruction allows to read the memory in QIO-SPI
protocol, parallelizing the instruction code, the address and the output data on four pins
(DQ0, DQ1, DQ2 and DQ3). The Quad Command Fast Read (QCFR) instruction can be
issued, after the device is set in QIO-SPI mode, by sending to the memory indifferently one
of the 3 instructions codes: 0Bh, 6Bh or EBh, the effect is exactly the same. The 3
instruction codes are all accepted to help the application code porting from Extended SPI
protocol to QIO-SPI protocol.
Apart for the parallelizing on four pins of the instruction code, the Quad Command Fast
Read instruction functionality is exactly the same as the Quad I/O Fast Read of the
Extended SPI protocol, please refer to Section 9.1.7: Quad I/O Fast Read for further details.
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