N25Q128 Datasheet, PDF (20/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

SPI Modes
N25Q128 - 1.8 V
(C_p = parasitic capacitance of the bus line) is shorter than the time during which the bus
master leaves the SPI bus in high impedance.
Example: C_p = 50 pF, that is R*C_p = 5 µs <=> the application must ensure that the bus
master never leaves the SPI bus in the high impedance state for a time period shorter than
5 µs. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as
appropriate.
Figure 6. Extended SPI protocol example
CPOL CPHA
0
0
C
1
1
C
DQ0
MSB
DQ1
MSB
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