N25Q128 Datasheet, PDF (147/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q128 - 1.8 V
Figure 88. Read Status Register instruction sequence QIO-SPI
Instructions
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
C
Instruction
Status Register Out
DQ0
4040 404040404040
DQ1
5151 515151515151
DQ2
6262 626 262626262
DQ3
7 3 7 3 7 37 3 7 3 7 3 7 37 3
Quad_Read_SR
9.3.14
Write status register (WRSR)
The write status register (WRSR) instruction allows new values to be written to the status
register. Before it can be accepted, a write enable (WREN) instruction must previously have
been executed.
The instruction code and the input data are sent on four pins DQ0, DQ1, DQ2 and DQ3. The
instruction functionality is exactly the same as the Write Status Register (WRSR) instruction
of the Extended SPI protocol (See Section 9.1.23: Write status register (WRSR)). However,
the protection feature management is different. In particular, once SRWD bit is set to '1' the
device enters in the hardware protected mode (HPM) independently from Write Protect
(W/VPP) signal value. To exit the HPM mode is needed to switch temporarily to the
Extended SPI protocol.
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