N25Q128 Datasheet, PDF (93/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q128 - 1.8 V
Instructions
9.1.13
Dual Input Extended Fast Program
The Dual Input Extended Fast Program (DIEFP) instruction is very similar to the Dual Input
Fast Program (DIFP), except that the address bits are shifted in on two pins (pin DQ0 and
pin DQ1) instead of only one.
Figure 22. Dual Input Extended Fast Program instruction sequence
S
Mode 3
C _{Mode 0}
DQ0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Instruction
642064206420
DQ1
S
C
7531 7531 7531
Address
Dummy Cycles
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
DQ0
DQ1
9.1.14
642064206420 6420
Data In 1
Data In 2
Data In 3
Data In 4
7531753175317531
MSB
MSB
MSB
MSB
6420
Data In 256
7531
MSB
Dual_Input_Extended_Fast_Program
Quad Input Fast Program
The Quad Input Fast Program (QIFP) instruction is very similar to the Dual Input Fast
Program (DIFP) instruction, except that the data are entered on four pins (pin DQ0, pin
DQ1, pin W/VPP/DQ2 and pin HOLD/ (DQ3) instead of only two. Inputting the data on four
pins instead of two doubles the data transfer bandwidth compared to the Dual Input Fast
Program (DIFP) instruction.
The Quad Input Fast Program (QIFP) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, three address bytes and at least one data byte on Serial
Data input (DQ0).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
93/185