N25Q128 Datasheet, PDF (115/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q128 - 1.8 V
Instructions
9.2.1
1) The number of Dummy Clock cycles is configurable by the user
2) SSE is only available in devices with Bottom or Top architecture.
Multiple I/O Read Identification protocol
The Multiple Input/Output Read Identification (MIORDID) instruction allows to read the
device identification data in the DIO-SPI protocol:
– Manufacturer identification (1 byte)
– Device identification (2 bytes)
Unlike the RDID instruction of the Extended SPI protocol, the Multiple Input/Output
instruction can not read the Unique ID code (UID) (17 bytes).
For further details on the manufacturer and device identification codes please refer to
Section 9.1.1: Read Identification (RDID).
Any Multiple Input/Output Read Identification (MIORDID) instruction while an Erase or
Program cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in parallel on the 2 pins DQ0 and DQ1. After this, the 24-bit
device identification, stored in the memory, will be shifted out on again in parallel on DQ1
and DQ0. Each two bits are shifted out during the falling edge of Serial Clock (C).
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Figure 44. Multiple I/O Read Identification instruction and data-out sequence DIO-
SPI
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
MAN.
DEV.
SIZE
AFh
code
code
code
DQ0
642064206420
DQ1
753175317531
Dual_Multi_Read_IO
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