N25Q128 Datasheet, PDF (46/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Volatile and Non Volatile Registers
N25Q128 - 1.8 V
6.5.4
6.5.5
6.5.6
The Erase Status bit is related to all possible erase operations: Sector Erase, Sub Sector
Erase, and Bulk Erase in all the three available protocols (SPI, DIO-SPI and QIO-SPI).
Once the bit 5 is set High, it can only be reset Low (FSR<5>=0) by a Clear Flag Status
Register command (CLFSR).
If set High it should be reset before a new Erase command is issued; otherwise the new
command will appear to fail.
Program Status bit
The bit 4 of the Flag Status Register represents the Program Status bit. It indicates:
„ a Program failure
„ an attempt to program a '1' on '0' when VPP=VPPH (only when the pattern is a multiple
of 64 bits, otherwise this bit is "Don't care").
„ a protection error when a program is issued
When the Program Status bit is High (FSR<4>=1) after a Program failure that means that
the P/E Controller has applied the maximum pulses number to the bytes and it still failed to
verify that the required data have been correctly programmed.
After an attempt to program '1' on '0', the FSR<4> only goes High (FSR<4>=1) if
VPP=VPPH and the data pattern is a multiple of 64 bits: if VPP is not VPPH, FSR<4>
remains Low and the attempt is not shown while if VPP is equal to VPPh but the pattern is
not a 64 bits multiple the bit 4 is Don't Care. The Program Status bit should be read once the
P/E Controller Status bit is High.
The Program Status bit is related to all possible program operations in the Extended SPI
protocol: Page Program, Dual and Quad Input Fast Program, Dual and Quad Input
Extended Fast Program, and OTP Program.
The Program Status bit is related to the following program operations in the DIO-SPI and
QIO-SPI protocols: Dual and Quad Command Page program and OTP program.
Once the bit is set High, it can only be reset Low (FSR<4>=0) by a Clear Flag Status
Register command (CLFSR). If set High it should be reset before a new Program command
is issued, otherwise the new command will appear to fail.
VPP Status bit
The bit 3 of the Flag Status Register represents the VPP Status bit. It indicates an invalid
voltage on the VPP pin during Program and Erase operations. The VPP pin is sampled at
the beginning of a Program or Erase operation.
If VPP becomes invalid during an operation, that is the voltage on VPP pin is below the
VPPH Voltage (9V), the VPP Status bit goes High (FSR<3>=1) and indeterminate results
can occur.
Once set High, the VPP Status bit can only be reset Low (FSR<3>=0) by a Clear Flag Status
Register command (CLFSR). If set High it should be reset before a new Program or Erase
command is issued, otherwise the new command will appear to fail.
Program Suspend Status bit
The bit 2 of the Flag Status register represents the Program Suspend Status bit, It indicates
that an Program operation has been suspended or is going to be suspended.
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