N25Q128 Datasheet, PDF (162/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

XIP Operations
Figure 102. N25Q128 Read functionality Flow Chart
Power On
NVCR Check
N25Q128 - 1.8 V
Is XIP enabled ?
Yes
No SPI standard mode (no
XiP, VCR <3> = 1)
XIP mode
No
Yes
XiP Confirmation
bit = 0 ?
VCR<3> = 0 ?
SPI mode (no XIP) but
Yes ^{ready to enter XIP}
No
No
Read Instructions ?
Yes
No
XiP Confirmation
bit = 0 ?
Yes
10.1
Enter XIP mode by setting the Non Volatile Configuration
Register
To use the Non Volatile Configuration Register method to enter in XIP mode it is necessary
to set the Non Volatile Configuration Register bits from 11 to 9 with the pattern
corresponding to the required XIP mode by mean of the Write Non Volatile Configuration
Register (WRNVCR) instruction. (See Table 25.: NVCR XIP bits setting example.)
This instruction doesn't affect the XIP state until the next Power on sequence. In this case,
after the next power on sequence, the memory directly accept addresses and then, after the
dummy clock cycles (configurable), outputs the data as described in Table 25.: NVCR XIP
bits setting example. For example to enable fast POR and XIP on QIOFR in normal SPI
protocol with six dummy clock cycles the following pattern must be issued:
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