N25Q128 Datasheet, PDF (38/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Volatile and Non Volatile Registers
N25Q128 - 1.8 V
6.2.2
6.2.3
6.2.4
6.2.5
Note:
6.2.6
XIP NV configuration bits (NVCR bits from 11 to 9)
The bits from 11 to 9 of the Non Volatile Configuration register store the default settings for
the XIP operation, allowing the memory to start working directly on the required XIP mode
after successive POR sequence: the device then accepts only address on one, two, or four
wires (skipping the instruction) depending on the NVCR XIP bits settings.
The default settings for the XIP bits of the NVCR enable the memory to start working in
Extended SPI mode after the POR sequence (XIP directly after POR is disabled).
Output Driver Strength NV configuration bits (NVCR bits from 8 to 6)
The bits from 8 to 6 of the Non Volatile Configuration register store the default settings for
the output driver strength, enabling to optimize the impedance at Vcc/2 output voltage for
the specific application.
The default values of Output Driver Strength bits of the NVCR set the output impedance at
Vcc/2 equal to 30 Ohms.
Fast POR NV configuration bit (NVCR bit 5)
The bit 5 of the NVCR enables the FAST POR sequence to speed up the application boot
phase before the first READ instruction: if enabled, the FAST POR allows to perform the first
read operation after less than 100us. Please note that this timing is valid only for the reading
operations: if a modify instruction is then required, after the first WREN instruction the
complete POR phase will be performed, resulting in latency time between the WREN and
the receiving of the modify instruction (~500us). During this latency time, when the power on
second phase is running, no instruction will be accepted except the standard polling
instructions either on the Flag Status register or in the Status Register.
The default values of Fast POR bit of the NVCR is set to disable the Fast POR feature, in
this case the POR sequence requires the standard value of ~500us and after the first
WREN instruction no relevant latency time is needed.
Hold (Reset) disable NV configuration bit (NVCR bit 4)
The Hold (RESET) disable bit can be used to disable the Hold (Reset) functionality of the
Hold (Reset) / DQ3 pin as described in Table 4.: Non-Volatile Configuration Register. This
feature can be useful to avoid accidental Hold or Reset condition entries in applications that
never require the Hold (Reset) functionality.
The default values of Hold (Reset) bit of the NVCR is set to enable the Hold (Reset)
functionality.
Reset functionality is available instead of Hold in devices with a dedicated part number. See
Section 16: Ordering information.
Quad Input NV configuration bit (NVCR bit 3)
The Quad Input NV configuration bit can be used to make the memory start working in QIO-
SPI protocol directly after the power on sequence. The products are delivered with this set
to 1, making the memory default in Extended SPI protocol, if the application sets this bit to 0
the device will enter in QIO-SPI protocol right after the next power on.
Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 3 and bit 2 of the
Non Volatile Configuration Register set to 0), the memory will work in QIO-SPI.
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