N25Q128 Datasheet, PDF (37/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q128 - 1.8 V
Volatile and Non Volatile Registers
Table 4. Non-Volatile Configuration Register
Bit
Parameter Value
Description
NVCR<5>
111
0
Fast POR x
READ
1
30 (default)
Enabled
Disabled (default)
NVCR<4>
NVCR<3>
NVCR<2>
NVCR<1:0>
Reset/Hold ⁰
disable
1
Quad Input ⁰
Command ₁
Dual Input ⁰
Command ₁
Reserved
xx
disabled
enabled (default)
enabled
disabled (default)
enabled
disabled (default)
Don't care
Note
POR phase < 100us only read available
POR phase ~ 700us all instructions
available
Disable Pad Hold/Reset functionality
Enable command on four input line
Enable command on two input line
Default value = "11"
6.2.1
Dummy clock cycle NV configuration bits (NVCR bits from 15 to 12)
The bits from 15 to 12 of the Non Volatile Configuration register store the default settings for
the dummy clock cycles number after the fast read instructions (in all the 3 available
protocols). The dummy clock cycles number can be set from 1 up to 15 as described here,
according to operating frequency (the higher is the operating frequency, the bigger must be
the dummy clock cycle number) to optimize the fast read instructions performance.
The default values of these bits allow the memory to be safely used with fast read
instructions at the maximum frequency (108 MHz). Please note that if the dummy clock
number is not sufficient for the operating frequency, the memory reads wrong data.
Table 5.
Maximum allowed frequency (MHz)
Maximum allowed frequency (MHz)⁽¹⁾
Dummy Clock
FASTREAD
DOFR
DIOFR
QOFR
1
50
50
39
43
2
95
85
59
56
3
105
95
75
70
4
108
105
88
83
5
108
108
94
94
6
108
108
105
105
7
108
108
108
108
8
108
108
108
108
9
108
108
108
108
10
108
108
108
108
1. All values are guaranteed by characterization and not 100% tested in production.
QIOFR
20
39
49
59
69
78
86
95
105
108
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