N25Q128 Datasheet, PDF (138/185 Pages) Numonyx B.V – 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q128 - 1.8 V
Figure 76. Read OTP instruction and data-out sequence QIO-SPI
S
0 1 2 3 4 5 6 7 8 9 10 15 16 17 18 19 20 21 22 23
C
Instruction
DQ0
4040 40
Data Data
out 1 out n
404040
DQ1
5151 51
DQ2
6262 62
515151
6 26262
DQ3
7373 73
737373
9.3.4
Dummy (ex.: 10)
Quad_Read_OTP
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. Apart form the
parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the
instruction functionality is exactly the same as the Write Enable instruction of the Extended
SPI protocol, please refer to Section 9.1.9: Write Enable (WREN) for further details.
Figure 77. Write Enable instruction sequence QIO-SPI
S
01
C
Instruction
DQ0
DQ1
DQ2
DQ3
Quad_Write_Enable
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