NS32FX100-15 Datasheet, PDF (8/94 Pages) National Semiconductor (TI) – System Controller

1 0 Fax-System Configuration (Continued)
The NS32FX100 modules and their functions are summa-
rized below For a more detailed description of each mod-
ule see the relevant section
1 2 1 Bus and Memory Controller (BMC)
The Bus and Memory Controller (BMC) interfaces directly to
the NS32FX161 the NS32FV16 or the NS32FX164 It en-
ables the NS32FX100 to respond to both read and write
transactions and to generate DMA transactions It divides
the address space into four external zones and generates
wait states and idle cycles according to the addressed
zone type of transaction and the programmed wait value
The memory controller directly interfaces to ROMs and
SRAMs The memory controllers of the NS32FX200 and the
NS32FV100 in addition directly interface to DRAMs
1 2 2 Timing Control Unit (TCU)
The Timing Control Unit (TCU) contains three blocks An
oscillators block generates the CPU high-speed clock and
the time-keeper clock The TCU module keeps trace of
elapsed time during all operation modes A counters block
contains timers counters for the various FAX-system con-
troller operations
1 2 3 Sigma-Delta CODEC (SDC)
The Sigma-Delta CODEC (SDC) interfaces with the tele-
phone line via an external Data Access Arrangement (DAA)
performing analog-to-digital and digital-to-analog conver-
sions data sampling and buffering Off-hook control and
ring-detect monitoring are performed by the Ports module
1 2 4 Scanner Controller (SCANC)
The Scanner Controller (SCANC) contains the video han-
dling block the scanner signals generator and the stepper
motor control block The block includes both analog and
digital circuits It uses DMA channel 0 to fetch a reference
line from memory and DMA channel 2 to store the digitized
video data to memory
1 2 5 Printer Controller (PRNTC)
The Printer Controller (PRNTC) contains the printer bitmap
shifter the stepper motor control block the temperature-
sensing block and the thermal print head control block It
uses DMA channel 1 to fetch the bitmap from memory
1 2 6 DMA Controller (DMAC)
NS32FX200 The DMA Controller (DMAC) provides four in-
dependent channels for transferring blocks of data between
memory and I O devices with minimal CPU intervention
Two channels are used for scanner control one for printer
control and one is available for external usage
NS32FX100 NS32FV100 The DMA Controller (DMAC) pro-
vides three independent channels for transferring blocks of
data between memory and I O devices with minimal CPU
intervention Two channels are used for scanner control
one for printer control
1 2 7 Universal Asynchronous Receiver-Transmitter
(UART)
The Universal Asynchronous Receiver-Transmitter (UART)
supports 7-bit or 8-bit data formats with or without parity
with or without hardware flow control and with one or two
stop bits The baud rate is generated on-chip under soft-
ware control
1 2 8 MICROWIRE (MWIRE)
The MWIRE is a serial synchronous communication inter-
face It enables the CPU to interface with any of National
Semiconductor’s chips which support MWIRE such as
COP400 COP800 and EEPROMs The MWIRE interface
consists of three signals serial data in serial data out and
shift clock Several devices can share the MWIRE channel
using selection signals provided by the Ports module
1 2 9 Interrupt Control Unit (ICU)
The Interrupt Control Unit (ICU) receives internal and exter-
nal interrupt sources and generates an interrupt to the CPU
when required Priority is allocated according to a predeter-
mined scheme The ICU supports programmable triggering
mode and polarity Each interrupt source can be individually
enabled or disabled Pending interrupts can be polled re-
gardless of whether they are enabled or disabled
1 2 10 Ports
The Ports module controls the usage of general-purpose
input and output pins The pins are shared with other mod-
ules and can be configured either as general-purpose I O
pins or as pins that belong to other modules An input port
always holds the current value state of its associated pins
Output pins can be enabled or disabled (TRI-STATE )
The number of general-purpose output pins can easily be
increased using an external latch (e g DM74LS373)
1 3 OPERATION MODES
The NS32FX100 operates in one of three modes
 Normal Mode
The CPU operates at the full clock fre-
quency Maximum current consump-
tion is 200 mA
 Power Save Mode The CPU runs at 1 16 of the Normal
mode frequency DMA channels must
be disabled output ports must be TRI-
STATE and MCFG except for bit 0
must be cleared Maximum current
consumption is 17 mA
 Freeze Mode
The CPU is frozen by active reset and
frozen clock it is not connected to the
backup battery The NS32FX100 chip
keeps track of elapsed time The
NS32FX200 and NS32FV100 can if
required refresh the memories Maxi-
mum current consumption is 1 mA with
refresh and 0 1 mA without refresh
In normal operation (see Figure 1-5 ) when reset is assert-
ed the NS32FX100 enters S6 of the Power Save mode
Switching from Power Save to Normal mode is carried out
by software
An RC circuit may be used to generate the CPU’s input
reset signal The WATCHDOG trap signal (WDT) generated
by the NS32FX100 may also force active CPU’s input reset
The NS32FX100 receives its reset from the CPU output re-
set signal This line should be pulled down by a resistor to
force reset in case the CPU is not powered
Failure of the main power source is detected externally (see
Figure 1-6 ) The CPU is notified by a non-maskable inter-
rupt The NS32FX100 is also notified that power has failed
through the PFAIL input pin The NS32FX100 power source
should be externally switched to the backup battery The
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