NS32FX100-15 Datasheet, PDF (37/94 Pages) National Semiconductor (TI) – System Controller

2 0 Architecture (Continued)
A transmit interrupt is generated on transmit ready if not
masked by the UMASK register A receive interrupt is gener-
ated if not masked by the UMASK register on receive
ready for every received character regardless of the occur-
rence of a reception error A reception error has no effect
on the current or the next data reception i e the current
data is available in the data buffer and the next data recep-
tion will occur in the usual way
No reception is enabled during break on the UART Receive
(URXD) pin A high-to-low transition is therefore required to
detect a start bit
The UART data buffers are eight bits wide
Whenever a new character is received and the data buffer
is empty the data buffer and the status register are updat-
ed Hardware flow control can be implemented either by
software (using the Ports module) or by hardware When
controlled by hardware transmission starts only if the
Transmit Enable input pin (UTEN) is asserted low Once a
byte transmission starts the UTEN value is ignored till the
stop bit is transmitted
The Receive Enable output pin (UREN) is inactive (high)
when both the receiver shifter and buffer are full UREN is
asserted low when the buffer or the shifter is empty
2 7 3 Registers
URXB Reception data buffer Read only 8-bit register
Bit 0 is the first bit serially received
Bit 7 is cleared during reception of 7-bit charac-
ters
Reading URXB updates the UCLST RF status bit
If a new character is ready in the shifter the
URXB is updated with the new value after the
current value has been read
UTXB
UBRGL
UBRGH
UCNTL
UMASK
Transmission data buffer 8-bit register
Bit 0 is the first bit serially transmitted
Bit 7 is ignored during transmission of 7-bit char-
acters
Low byte of the CTTL clock divider (UBRG) 8-bit
register
High byte of the CTTL clock divider (UBRG) 8-bit
register
These two one-byte registers are used to gener-
ate a clock whose frequency is 16 times the
baud rate according to the following equation
CTTL (UBRG a 1) e baud-rate 16
UART Control register
Controls the number of data and stop bits parity
enable disable and odd even and break trans-
mission on off Upon reset all the non reserved
bits are cleared to ‘‘0’’
UART Mask Interrupts register Upon reset the
implemented bits are cleared to ‘‘0’’
7
21
0
res
MTI MRI
MTI Mask Transmit Interrupt
0 Transmit Interrupt is not masked
1 Transmit Interrupt is masked
MTI Mask Receive Interrupt
0 Receive Interrupt is not masked
1 Receive Interrupt is masked
FIGURE 2-20 Character Format
TL EE 11331 – 25
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