NS32FX100-15 Datasheet, PDF (77/94 Pages) National Semiconductor (TI) – System Controller

4 0 Device Specifications (Continued)
4 6 2 Timing Tables (Continued)
4 6 2 2 Input Signal Requirements (Continued)
Symbol Figure Description
Reference
Condition
NS32FX200-15
Min
Max
NS32FX200-20
Min
Max
NS32FX200-25
Min
Max
Units
t_ADSs
4-9 ADS Signal
Before R E
51
36
27
ns
Setup
CTTL T2
t_ADSw
4-9 ADS Pulse
At 0 8V
20
15
10
ns
Width
(Both Edges)
t_Ds
4-16 Data Setup
Before R E
15
14
10
ns
CTTL T4
t_Dh
4-16 Data Hold
After R E
0
0
0
ns
CTTL T4
t_HBEs
4-9 HBE Signal
Before R E
51
36
27
ns
Setup
CTTL T2
t_HBEh
4-9 HBE Signal
After R E
0
0
0
ns
Hold
CTTL next T1 i
t_DDINs
4-9 DDIN Signal
Before R E
51
36
27
ns
Setup
CTTL T2
t_DDINh
4-9 DDIN Signal
After R E
0
0
0
ns
Hold
CTTL next T1 i
t_HLDAs 4-16 HLDA Signal
Before R E
51
36
27
ns
Setup
CTTL Ti
t_HLDAh 4-16 HLDA Signal
After R E
0
0
0
ns
Hold
CTTL Ti
t_SDINs 4-19 SDIN Signal
Before F E
15
14
ns
12
Setup
CTTL
t_SDINh 4-19 SDIN Signal
After F E
0
0
0
ns
Hold
CTTL
t_SVIs
4-27 SVI Signal Setup After L E
(Notes 1 2)
SNH
t_SCMPRW
b 200 ns
t_SCMPRW
b 200 ns
t_{SCMPRW ns}
b 200 ns
t_SVIh
4-27 SVI Signal
After L E
0
0
0
ns
Hold
Next SNH
t_SBGs
4-27 SBG Signal Setup After L E
(Notes 1 2)
SNH
t_SCMPRW
b 200 ns
t_SCMPRW
b 200 ns
t_{SCMPRW ns}
b 200 ns
t_SBGh
4-27 SBG Signal
After L E
0
0
0
ns
Hold
Next SNH
t_PFAILs 4-22 PFAIL Signal
Before R E
15
14
13
ns
Setup
CTTL
t_PFAILh 4-22 PFAIL Signal
After R E
0
0
0
ns
Hold
CTTL
t_INTs
4-18 INT0–3 Signal Before R E
15
14
13
ns
Setup
CTTL
t_INTh
4-18 INT0–3 Signal After R E
0
0
0
ns
Hold
CTTL
Note 1 t_SCMPRW e (SCMPRW a 1) t_CTp while SCMPRW is the programmed value in SCMPRW register The current tolerance is 8 mA
Note 2 The internal analog reset width as programmed in the SCMPRW register should be more than 200 ns The analog reset should be terminated at least 300
ns before the next SNH leading edge
77