NS32FX100-15 Datasheet, PDF (11/94 Pages) National Semiconductor (TI) – System Controller

2 0 Architecture (Continued)
2 2 2 1 External Clocks
The TCU contains two oscillators the high-speed oscillator
and the low-speed oscillator The high-speed oscillator is
the FAX system clocking source It generates the CPU clock
and after division clocks for the Sigma-Delta CODEC
scanner printer and serial communications channels A
high-speed clock signal is input to the NS32FX100 from an
external crystal through the FOSCI pin The NS32FX100
uses this signal to generate the CCLK clock which serves
as the input clock to the CPU The CPU then divides CCLK
by two and generates CTTL which serves as the bus clock
The NS32FX100 includes a PLL to ensure synchronization
between the NS32FX100 clocks and the CPU CTTL is used
to close the PLL loop and enable tracking of the CPU inter-
nal clocks
The low-speed oscillator which gets its input through the
SOSCI pin is used to keep track of elapsed time and to
operate the refresh requester This oscillator operates in
Normal mode as well as in Power Save and Freeze modes
The NS32FX100 controls the CPU running frequency It
may reduce the frequency by dividing CCLK by 16 To en-
sure accurate tracking of the CTTL phase by the
NS32FX100 clock division should be carried out via the
NS32FX100 and the power save mode of the CPU should
not be used
The slow oscillator which operates during Normal Power
Save and Freeze modes can be a 32 768 kHz oscillator for
systems with memory refresh rate of up to 8 kHz Systems
with memory refresh rate higher than 8 kHz should use a
slow oscillator of 455 kHz
2 2 2 2 Internal Clocks
The TCU module generates a 1 2288 MHz Master Clock
(MCLK) MCLK is generated by a programmable divider
which divides the CTTL input clock The MCLK clock is used
for synchronization throughout the NSFX100-based FAX
system In particular the following are derived from MCLK
 CLK128 A 12 8 kHz clock
 Time-Slots generator (TSL) An 8-bit down counter fed
by CLK128
The Time-Slots generator performs two functions
 Division of each 20 ms period into 256 time slots
 Generation of a 100 Hz System Tick (STIC)
The time slots are used to synchronize the various compo-
nents of the FAX system e g the printer and scanner with
their respective motors
The System Tick is used by both the Interrupt Control Unit
(ICU) for generating an interrupt and by the WATCHDOG
counter as described in Section 2 2 3
Several registers are provided to control and use the TCU
and I O signals These registers are described in Section
223
Note 1 When CSCL e 1 CLK128 is generated by dividing MCLK by 6
Note 2 When CSCL e 0 CLK128 is generated by dividing MCLK by 96
(MCLK is 1 2288 MHz refer to Table I for MCLON and MCLOFF values)
Note 3 CLK128 is always 12 800 Hz and STIC is always 100 Hz
FIGURE 2-2 High Speed Oscillator Clocks
TL EE 11331 – 7
FIGURE 2-3 Low Speed Oscillator Clocks
11
TL EE 11331 – 8