NS32FX100-15 Datasheet, PDF(31/94 Page) National Semiconductor (TI)

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NS32FX100-15 Datasheet, PDF (31/94 Pages) National Semiconductor (TI) – System Controller

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2 0 Architecture (Continued)

DEC

NFBY

DIR

ADA

ADCA

ADRA

ADRB

BLTC

BLTR

Decrement Increment update of ADCA

0 ADCA incremented after each transfer cycle (if

ADA e 1)

1 ADCA decremented after each transfer cycle (if

ADA e 1)

Fly-By Memory-to-I O Transfers for channel 3

only (for channels 0 1 2 reserved)

0 Fly-By

1 Memory-to-I O

Transfer Direction

Specifies the direction of the transfer between

memory and implied I O device

0 Implied I O Device is Destination

1 Implied I O Device is Source

Device Address Control Controls the update of the

ADCA counter after each transfer cycle

0 ADCA address unchanged

1 ADCA address updated

Device Address Counter 32-bit register

Bits 0â23

Hold the current address of either the

source data item or the destination lo-

cation in the Addressed Device

Bits 24â31 Reserved

If the ADA bit in the MODE register is

set to ââ1ââ ADCA is updated accord-

ing to DEC and FBY bits in MODE reg-

ister after every DMA transfer

Device Address Register 32-bit register (Channels

1 and 3 only)

Bits 0â23

Hold the starting address of the next

block to be transferred of either the

source data block or the destination

data area of the Addressed Device

Bits 24â31 Reserved

Implied I O Device register 32-bit register (Chan-

nel 3 only)

Bits 0â23

Hold the address of either the source

data block or the destination data

area of the implied I O device

Bits 24â31 Reserved

Block Length Counter 32-bit register

Bits 0â23 Hold the current number of bytes to

be transferred

Bits 24â31 Reserved

BLTC is decremented after each transfer accord-

ing to FBY bit in MODE register

Block Length Register 32-bit register (Channels 1

and 3 only)

Bits 0â23 Hold the number of bytes in the next

block to be transferred

Bits 24â31 Reserved

A ââ0ââ value in the BLTR register while the VLD

and CHEN in the CNTL register are both set to ââ1ââ

may cause unpredictable results

STAT

Res

Status register This register has two functions

Holds status information for the DMA channel

Used to enable or mask the DMA interrupts for the

various terminations conditions

EOVR res

ETC CHAC OVR

res

OVR

CHAC

ETC

EOVR

Terminal Count

When set to ââ1ââ indicates that the transfer was

completed by a terminal count condition (BLTC)

reached 0)

Channel Overrun (Channels 1 3 only)

Set to ââ1ââ in non auto-initialize mode when the

present transfer is completed (BLTC e 0) but the

parameters for the next transfer are not valid (VLD

bit in CNTL is ââ0ââ)

Channel Active Read Only

When set to ââ1ââ indicates that the channel is ac-

tive (CHEN bit in CNTL register is ââ1ââ and BLTC l

This bit continuously reflects the active or inactive

status of the channel and therefore can only be

read Data written to the CHAC bit is ignored

Enables interrupt pulse when the BLTC counter

reaches 0

0 Disable

1 Enable

Enables interrupt pulse when OVR bit is set (Chan-

nels 1 3 only)

0 Disable

1 Enable

The TC and OVR bits are sticky This means that once set

by the occurrence of the specific condition they will remain

set until explicitly cleared by software Those bits can be

individually cleared by writing a value into the STAT register

with the bit positions to be cleared set to ââ1ââ Writing ââ0ââ to

those bits has no effect

CNTL

Control register

This register is used to synchronize the channel

operation with the programming of the block trans-

fer parameters

res

VLD CHEN

CHEN

Channel Enable

0 Channel Disable

1 Channel Enable

The CHEN bit is cleared to ââ0ââ in the following

cases

(1) Upon Reset

(2) Software clears it by writing to the CNTL regis-

ter

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