NS32FX100-15 Datasheet, PDF (78/94 Pages) National Semiconductor (TI) – System Controller

4 0 Device Specifications (Continued)
4 6 2 Timing Tables (Continued)
4 6 2 2 Input Signal Requirements (Continued)
Symbol Figure
Description
Reference
Condition
NS32FX200-15
Min
Max
NS32FX200-20
Min
Max
t_URXDs 4-24 URXD Signal
Before R E
15
14
Setup
CTTL
t_URXDh 4-24 URXD Signal
After R E
0
0
Hold
CTTL
t_UTENs
4-24 UTEN Signal
Setup
Before R E
CTTL
t_{CTp 2}
a15
t_{CTp 2}
a14
t_UTENh
4-24 UTEN Signal
Hold
After R E
CTTL
t_{CTp 2}
t_{CTp 2}
t_DMRQs 4-16 DMRQ0 – 3 Signal Before R E
30
29
Setup
CTTL
t_DMRQh 4-16 DMRQ0 – 3 Signal After R E
0
0
Hold
CTTL
t_MWSIs
4-25 MWSI Signal
Setup (Note 1)
Before R E
CTTL
t_{CTp 2}
a15
t_{CTp 2}
a14
t_MWSIh
4-25 MWSI Signal
Hold
After R E
CTTL
t_{CTp 2}
t_{CTp 2}
t_SBYPSs 4-23 SBYPS Signal
Before R E
30
29
Setup
CTTL
t_SBYPSh 4-23 SBYPS Signal
After R E
0
0
Hold
CTTL
t_PAs
4-26 Port A Signal
Before R E
t_{CTp 2}
Setup
CTTL
a15
t_{CTp 2}
a14
t_PAh
4-26 Port A Signal
Hold
After R E
CTTL
t_{CTp 2}
t_{CTp 2}
t_PCs
4-26 Port C Signal
Before R E
t_{CTp 2}
Setup (Note 2)
CTTL
a15
t_{CTp 2}
a14
t_PCh
4-26 Port C Signal
Hold
After R E
CTTL
t_{CTp 2}
t_{CTp 2}
Note 1 When configured as MWIRE signal MWSI is sampled on the first CTTL R E following the MWSK F E
Note 2 Includes all port C pins when configured as general purpose pins
NS32FX200-25
Min
Max
13
Units
ns
0
ns
t_{CTp 2}
ns
a13
t_{CTp 2}
ns
28
ns
0
ns
t_{CTp 2}
ns
a13
t_{CTp 2}
ns
28
ns
0
ns
t_{CTp 2}
ns
a13
t_{CTp 2}
ns
t_{CTp 2}
ns
a13
t_{CTp 2}
ns
78