NS32FX100-15 Datasheet, PDF (4/94 Pages) National Semiconductor (TI) – System Controller

List of Figures
FIGURE 1-1 A FAX Controller Block Diagram
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FIGURE 1-2 NS32FX100 Module Diagram
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FIGURE 1-3 NS32FV100 Module Diagram
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FIGURE 1-4 NS32FX200 Module Diagram
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FIGURE 1-5 System Chip States and Operation Modes
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FIGURE 2-1 Clocks and Traps Connectivity
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FIGURE 2-2 High Speed Oscillator Clocks
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FIGURE 2-3 Low Speed Oscillator Clocks
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FIGURE 2-4 Sigma-Delta Block Diagram
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FIGURE 2-5 SDC Off-Chip Analog Circuit
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FIGURE 2-6 Block Diagram of Scanner’s Signals Generator Block
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FIGURE 2-7 Scanner Pixel Control Signals
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FIGURE 2-8 Scanner Period Control Signals
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FIGURE 2-9 Block Diagram of Scanner’s Video Handling Block
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FIGURE 2-10 Dither Cyclic Buffer
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FIGURE 2-11 Bitmap Shifter Signals
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FIGURE 2-12 Four Strobes Mode (STBM e 00)
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FIGURE 2-13 Two Strobes Mode (STBM e 01)
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FIGURE 2-14 Temperature ADC
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FIGURE 2-15 DMA Fly-By Read Transaction (DIRe0 FBYe 0)
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FIGURE 2-16 DMA Fly-By Write Transaction (DIRe1 FBYe0)
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FIGURE 2-17 DMA Memory to I O Read Transaction (DIRe0 NFBYe1)
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FIGURE 2-18 DMA I O to Memory Write Transaction (DIRe1 NFBYe1)
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FIGURE 2-19 Two Adjacent Fly-By DMA Transactions
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FIGURE 2-20 Character Format
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FIGURE 2-21 MICROWIRE Transaction (CLKMe0)
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FIGURE 2-22 MICROWIRE Transaction (CLKMe1)
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FIGURE 2-23 Port A
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FIGURE 2-24 Port B
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FIGURE 2-25 Port C
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FIGURE 2-26 External Output Port Extension
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FIGURE 3-1 Power and Ground Connections
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FIGURE 3-2 Oscillator Circuits
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FIGURE 3-3 Zones 0 1 (ROM SRAM) Read Transaction Zero Wait State
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FIGURE 3-4 Zones 0 1 (ROM SRAM) Read Transaction One Wait State
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FIGURE 3-5 Zones 0 1 (ROM SRAM) Write Transaction Zero Wait State
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FIGURE 3-6 Zones 0 1 (ROM SRAM) Write Transaction One Wait State
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FIGURE 3-7 Zone 2 (DRAM) Refresh Transaction Zero Wait State
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FIGURE 3-8 Zone 2 (DRAM) Refresh Transaction Three Wait States
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FIGURE 3-9 Freeze Mode Refresh Transaction Waveform
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FIGURE 3-10 Zone 2 (DRAM) Read Transaction Zero Wait State
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FIGURE 3-11 Zones 0 1 Access Delayed by a Refresh Transaction (No Wait)
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FIGURE 3-12 Zone 2 (DRAM) Read Transaction One Wait State
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FIGURE 3-13 Zone 2 (DRAM) Write Transaction Zero Wait State
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FIGURE 3-14 Zone 2 (DRAM) Write Transaction One Wait State
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FIGURE 3-15 Zone 3 (I O) Read Transaction Two Wait States
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FIGURE 3-16 Zone 3 (I O) Read Transaction Four Wait States
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FIGURE 3-17 Zone 3 (I O) Write Transaction Four Wait States
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FIGURE 3-18 Zone 3 (I O) Write Transaction Six Wait States
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FIGURE 3-19 CPU DMA Arbitration
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FIGURE 3-20 Spaced Memory Transaction Two Tidles after T4
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