NS32FX100-15 Datasheet, PDF (23/94 Pages) National Semiconductor (TI) – System Controller

2 0 Architecture (Continued)
Pixel Generator
Pixels may be treated in one of three ways
No bypass
The output of the video comparator is an
image pixel It may be inverted by the pixel
generator before the pixel is shifted into the
bitmap shifter
Input bypass
(Available in the NS32FX200 only ) The vid-
eo comparator output is bypassed (the vid-
eo DAC output is taken through the SCVO
output pin to an external circuit) and an ex-
ternally generated pixel is taken as the input
to the pixel generator through the SBYPS
pin
Output bypass (Available in the NS32FX200 only ) As in the
No bypass case the comparator feeds the
bitmap shifter In addition the last sampled
pixel sampled on the last SNH leading edge
and inverted is driven onto the SBYPS pin
for optional use by an external circuit (e g
for edge emphasis)
The operation mode of the pixel generator in the
NS32FX200 is controlled by the Scanner Video Handling
Control register (SVHC) and Port C control registers (PCMS
PCEN) It must be configured as ‘‘No bypass’’ in the
NS32FX100 and NS32FV100
No bypass
SVHC BYPASS e 0 and
PCMS MS4 e 0
Input bypass
SVHC BYPASS e 1 and
PCMS MS4 e 1 and
PCEN EN4 e 0
Output bypass
SVHC BYPASS e 0 and
PCMS MS4 e 1 and
PCEN EN4 e 1
Note that the pin output value is unpredictable if the scanner
module is disabled (MCFG ESCAN e 0) while both
PCMS MS4 and PCEN EN4 are set
The pixel generator can be configured to invert a pixel be-
fore it is shifted
Bitmap Shifter
The pixel generator output is accumulated and stored into
memory via DMA channel 2 Pixels are shifted from left to
right i e The first pixel in each word is the Least Significant
Bit (LSB) The bitmap is double buffered by the Scanner
Bitmap Shifter (SBMS) and a word buffer between the scan-
ner module and the DMA channel The shifter operation is
enabled during active window only and clocked by SNH
leading edge In order to allow software intervention in col-
lecting the scanner’s bitmap the shifter is readable by soft-
ware
2 4 2 5 Stepper Motor Control Block
The stepper motor is controlled by four phases The motor
direction and speed is controlled by setting or clearing
each phase as scanning progresses The motor is con-
trolled by setting the time-slots in which the phases should
be changed (in the SMTSL register) When the set time-slot
is reached an interrupt is generated and the phase values
are updated to the values in the phase register (SMPH) in
the Ports module
2 4 3 Registers
SPRES
Scanner SPCLK Prescale 8-bit register
One SPCLK cycle time equals (SPRES a 1)
CTTL cycles
SDISD
Scanner Discharge Delay Write only 8-bit reg-
ister
Controls the delay between the edge of SCLK1
and the leading edge of the SDIS signal The
delay is (SDISD a 1) CTTL cycles
SDISW
Scanner Integrator Discharge Pulse Width
Write only 8-bit register
The width is (SDISW a 1) CTTL cycles
SNHD
Scanner Sample and Hold Delay Write only
8-bit register
Controls the delay between the edge of SCLK1
and the leading edge of SNH signal The delay
is (SNHD a 1) CTTL cycles
SNHW
Scanner Sample and Hold Pulse Width Write
only 8-bit register
The width is (SNHW a 1) CTTL cycles
SCMPRW Scanner Comparator Preset Pulse Width Write
only 8-bit register
The width is (SCMPRW a 1) CTTL cycles
SLSD
Scanner Line Sync Delay Write only 8-bit regis-
ter
Controls the delay between the Scanner’s Peri-
od Pulse (SPP) and the leading edge of the SLS
signal
SLSW
Line Sync Pulse Width Write only 8-bit register
The width is (SLSW a 1) CTTL cycles
SAVWD
Active Video Window Delay Write only 16-bit
register
Controls the delay between the leading edge of
the Scanner’s Period Pulse (SPP) and the be-
ginning of the active video window (number of
ignored pixels)
SAVWW
Active Video Window Width Write only 16-bit
register
The width is (SAVWW a 1) SPCLK cycles
SPDWD
Peak Detector Window Delay Write only 16-bit
register
The delay between leading edge of Scanner’s
Period Pulse (SPP) and the beginning of peak
detector window
SPDWW
Peak Detector Window Width Write only 16-bit
register The width is (SPDWW a 1) SPCLK cy-
cles
SGC
Scanner Signals Generator Control register
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