NS32FX100-15 Datasheet, PDF (15/94 Pages) National Semiconductor (TI) – System Controller

2 0 Architecture (Continued)
A full Sigma-Delta CODEC includes a digital part and an
analog part The NS32FX100 includes the digital part and
the analog part should be implemented externally
2 3 2 2 On-Chip Digital Blocks
Sigma-Delta Over Sampling Rate (OSR) is 128 times the
Sampling Rate (SR) Some Sigma-Delta blocks use also
Double Sampling Rate (DSR)
For communication applications the SR is 9 6 kHz DSR is
19 2 kHz and the OSR is 1 2288 MHz For voice applica-
tions the SR is 8 kHz DSR is 16 kHz and the OSR is
1 024 MHz
DF (Decimation Filter) Receives 1-bit stream at OSR and
decimates it to 16-bit at DSR
IIR Filters The IIR filters include Transmission Reception
and Echo-canceler programmable filters The Echo-cancel-
ing filter can be bypassed
The Transmission IIR includes two filters The first
filter operates at SR The second filter interpolates
the data rate by two Thus the filter operates at
DSR
The Reception IIR includes two filters The first filter
operates at DSR and decimates the data rate by
two Thus the second filter operates at SR
The Echo-canceler filter works at DSR This filter is
used to cancel the echo path
Receive Gain Control (RGC) Amplifies or attenuates the
received data to achieve the required signal level con-
trolled by software Automatic Gain Control (AGC)
Transmit Gain Control (TGC) Attenuates the transmitted
data to achieve the required signal level controlled by soft-
ware Automatic Gain Control (AGC)
Digital Sigma-Delta (DSDM) Transforms the 16-bit trans-
mitted data at DSR into a 1-bit stream at OSR A second-or-
der digital Sigma-Delta circuit performs this function
Processor Interface (PI) Contains the SDC control and
data registers a 12-level transmission FIFO a 12-level re-
ception FIFO and a clock divider unit
2 3 3 Programmable Functions
The Sigma-Delta programming model consists of the follow-
ing elements
 IIR coefficients memory
 Data registers
 Control registers
2 3 3 1 Sigma-Delta ON OFF
The SDC module is enabled by MCFG ESDC control bit
When MCFG ESDC is ‘‘0’’ the SDC module is disabled
The user can access all SDC memory-mapped addresses
(IIR coefficients and SDC registers) only while MCFG ESDC
is active Any attempt to access SDC memory-mapped ad-
dresses while MCFG ESDC is ‘‘0’’ will cause an unpredict-
able result
To turn off SDC turn off receive mode (SDCNTL REe0)
and transmit mode (SDCNTL TEe0) and only then clear
MCFG ESDC to ‘‘0’’
2 3 4 Off-Chip Analog Circuits
The circuit required to connect the SDC on-chip module to a
2-wire line is shown in Figure 2-5 The components are de-
tailed in the following table
TABLE 2-2 Component Values
Component
Value
Tolerance
R1
600X
1%
R2
47 kX
5%
R3
47 kX
5%
R4
47 kX
5%
R5
330X
5%
R6
330X
5%
R7
15 4 kX
1%
R8
56 kX
5%
R9
100 kX
5%
R10
22 kX
5%
R11
22 kX
5%
R12
56 kX
5%
R13
5 1 kX
5%
R14
5 6 kX
5%
R15
1 0 kX
5%
R16
330X
5%
R17
330X
5%
R18
56 kX
5%
C1
0 1 mF
10%
C2
3 3 nF
10%
C3
100 pF
10%
C4
1 nF
10%
C5
22 mF
10%
C6
0 1 mF
10%
C7
22 mF
10%
C8
0 1 mF
10%
C9
47 pF
10%
C10
330 pF
10%
C11
200 pF
10%
C12
22 mF
10%
C13
0 1 mF
10%
C14
22 mF
10%
C15
0 1 mF
10%
C16
100 pF
10%
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