NS32FX100-15 Datasheet, PDF(40/94 Page) National Semiconductor (TI)

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NS32FX100-15 Datasheet, PDF (40/94 Pages) National Semiconductor (TI) – System Controller

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2 0 Architecture (Continued)

2 8 4 Usage Recommendations

1 Before activating the MICROWIRE program the appro-

priate Ports module registers PBDO PBMS PCDO

PCMS and PCEN to connect the MICROWIRE module to

the NS32FX100 I O pins

2 The correct sequence for a MWIRE transaction is to se-

lect a device issue the MWIRE transaction and then de-

select the device A device can be selected either by

using the Ports module or implicitly if only one device is

connected to the bus)

3 Writing to MWSIO register triggers the shift transaction

Reading the MWSIO does not trigger a shift transaction

but returns the current contents of the MWSIO For a

read transaction perform a dummy write transaction to

initiate the shift and then read the MWSIO i e write a

byte wait until not busy and then read the result

2 9 INTERRUPT CONTROL UNIT (ICU)

2 9 1 Features

Y 16 interrupt sources

Y Supports CPU vectored-interrupt mode

Y Fixed priority among interrupt sources

Y Individual enable disable of each interrupt source

Y Polling support by an interrupt pending register

Y Programmable triggering mode and polarity

2 9 2 Operation

The Interrupt Control Unit (ICU) receives interrupt signals

from internal and external sources and generates a vector

interrupt to the CPU when required Priority among the inter-

rupt sources if fixed Each interrupt source can be individu-

ally enabled or disabled Pending interrupts can be polled

using the interrupt pending register regardless of their being

enabled or disabled

The ICU triggering mode and polarity of each interrupt

source (individually) are both programmed via the Interrupt

Edge Level Trigger register (IELTG) and the Interrupt Trig-

ger Polarity register (ITRPL) Both the polarity and the trig-

gering mode of the interrupts that are generated on-chip are

fixed It is the softwareâs responsibility to program the re-

spective bits in IELTG and ITRPL as required

Edge-triggered interrupts are latched by the interrupt pend-

ing register A pending edge-triggered interrupt is cleared by

writing the required value to the edge interrupt clear regis-

ter A pending level-triggered interrupt is cleared only when

the interrupt source is not active

Interrupt vector numbers are always positive in the range

20(hex) to 2F(hex)

MCFG ESCAN bit controls the IRQ11 interrupt source

MCFG EDMA0 bit controls the IRQ13 interrupt source

TPHC PIS bit controls the IRQ14 interrupt source

The external interrupt inputs are asynchronous They are

recognized by the NS32FX100 during cycles in which the

input setup and hold time requirements are satisfied

IRQ0

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

IRQ8

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

Internal

External

Internal

External

Internal

External

Internal

External

TABLE 2-3 Interrupt Sources and Priority Levels

Level-High

Edge-Rising

Level-High

Edge-Rising

MICROWIRE

INT0 Pin

System Tick

TIMER Pulse

INT1 Pin

UART

SDC Transmit

SDC Receive

SDC Error

INT2 Pin

Printer Motor

Scanner Motor or DMA Channel 2

(Selected by MCFG)

DMA Channel 3

Scanner or DMA Channel 0 (Selected by

MCFG)

Printer or DMA Channel 1 (Selected by

TPHC)

INT3 Pin

Lowest Priority

Highest Priority

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