NS32FX100-15 Datasheet, PDF (36/94 Pages) National Semiconductor (TI) – System Controller

2 0 Architecture (Continued)
FIGURE 2-19 Two Adjacent Fly-By DMA Transactions
TL EE 11331 – 24
The maximum throughput of a DMA channel is 12 5 Mbyte sec (Two bytes can be transferred at a rate of four CTTL cycles per
transfer up to 25 MHz )
Note 1 Memory control signals (like CWAIT select and write enable) are generated according to the specifications of the accessed zone
v Note 2 A in the figure indicates DMA priority resolving points
2 7 UNIVERSAL ASYNCHRONOUS RECEIVER-
TRANSMITTER (UART)
2 7 1 Features
Y _{Full duplex double-buffered transmitter receiver}
Y _{Programmable baud rate between 300 and CTTL 32}
baud
Y _{Hardware flow control}
Y _{Asynchronous 7-bit or 8-bit character transmission}
reception
Y _{Supports transmission of one or two stop bits}
Y _{Hardware support of odd or even parity-bit generation}
during transmission
Y _{Hardware support of odd or even parity check during}
reception
Y _{Maskable interrupt on transmit ready or receive ready}
regardless of reception errors
Y _{Data sampled at 16 times the baud rate}
Y _{Software-controlled break transmission and detection}
2 7 2 Operation
The Universal Asynchronous Receiver Transmitter (UART)
module enables the NS32FX100 to communicate with stan-
dard serial devices using three communication signals
transmit receive and ground A character is composed of a
start bit followed by data bits (the least significant bit right
after the start bit) followed by an optional parity bit and at
least one stop bit The communication is serial the trans-
mit and receive signals hold one bit at a time Bit duration is
one baud time
The UART can be configured with the following communica-
tion parameters 7-bit or 8-bit data formats with or without
parity with one or two stop bits
Baud rate is generated internally by dividing CTTL under
software control Break is generated under software control
Break detection is via the frame error status bit (UCLST FE)
The UART is full-duplex it can transmit and receive charac-
ters simultaneously The software may use either polling or
interrupts to operate the UART Both transmission and re-
ception are double buffered to relax software response
time
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