NS32FX100-15 Datasheet, PDF (20/94 Pages) National Semiconductor (TI) – System Controller

2 0 Architecture (Continued)
2 4 2 2 Scanner Period Pulse (SPP) Generation
The Scanner Period Pulse (SPP) is used to synchronize all
the scanner control signals It is derived from the time slots
generated by the TCU module (which divides each 20 ms
into 256 time slots)
SPCLK Generation
The internal Scanner Pixel Clock (SPCLK) is generated by
dividing CTTL by a programmable prescale value The result
is a video clock which is twice the frequency of the scanner
clocks SPCLK is used for generation of other scanner sig-
nals The value of SPCLK should be determined according
to the scanner specification
The SPCLK pre-scale divider is reset by each SPP leading
edge As a result the first SPCLK cycle after the SPP may
be distorted Software should program the control registers
SAVWD SLSD and SPDWD so that the first pixel after the
SPP is ignored
SCLK1 and SCLK2 Generation
The two scanner clocks SCLK1 and SCLK2 are generated
by dividing SPCLK by two SCLK1 is high and SCLK2 is low
after SPP leading edge
SDIS and SNH Generation
The Integrator Discharge Pulse (SDIS) and the Sample-and-
Hold Control Clock (SNH) are generated by timers which
are clocked by CTTL and triggered by SPCLK For each of
these signals the polarity the delay (between SPCLK and
its leading edge) and the width are software programmable
The total number of delay and width cycles must not exceed
the number of CTTL cycles in one SPCLK period
Analog Comparator Preset Generation
The Analog Comparator Preset is an internal signal used to
initialize the on-chip analog comparator It is generated by a
timer clocked by CTTL and triggered by SNH leading edge
Note In this figure SDIS has inverted polarity (DISPe0)
FIGURE 2-7 Scanner Pixel Control Signals
TL EE 11331 – 12
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