NS32FX100-15 Datasheet, PDF (54/94 Pages) National Semiconductor (TI) – System Controller

3 0 System Interface (Continued)
3 4 BUS CYCLES
Memory transactions issued by the CPU and the
NS32FX100 are almost identical The transactions differ as
follows
1 During the CPU transactions data is driven onto AD0–15
throughout T4 whereas on DMA transactions by the
NS32FX100 data is not driven onto AD0–15 to the end
of T4
2 The NS32FX100 does not drive HBE and address on
AD0 – 15 during T1
3 The CPU drives ADS in T1 The NS32FX100 drives ADS
from Ti preceding T1 through T1
Read Transactions WEi inactive Only one SELi or RASi
active Write Transactions OE inactive Only one SELi or
RASi active
TL EE 11331 – 35
FIGURE 3-3 Zones 0 1 (ROM SRAM) Read Transaction Zero Wait State
FIGURE 3-4 Zones 0 1 (ROM SRAM) Read Transaction One Wait State
54
TL EE 11331 – 36