NS32FX100-15 Datasheet, PDF (72/94 Pages) National Semiconductor (TI) – System Controller

4 0 Device Specifications (Continued)
4 6 2 Timing Tables (Continued)
4 6 2 1 Output Signals Internal Propagation Delays (Continued)
Symbol Figure
Description
Reference
Condition
NS32FX200 – 15
Min
Max
NS32FX200 – 20
Min
Max
t_AHv
4-16 A16–23 Valid
After R E
CTTL T1
50
36
t_AHh
4-16 A16–23 Hold
After R E
0
0
CTTL T4 or Ti
t_WEa
4-10 WE0–1 Signal
Active
After R E
CTTL
20
17
t_WEia
4-10 WE0–1 Signal
Inactive
After R E
CTTL
t_{CTp 2}
t_{CTp 2}
a 20
t_{CTp 2}
t_{CTp 2}
a 17
t_WEw
4-10 WE0–1 Pulse
At 0 8V
80
61
Width (Note 2)
(both edges)
t_CWh
4-10 WE0–1 Signal
After F E
20
15
Hold (Notes 1 2) CAS
t_OEa
4-9 OE Signal
Active
After R E
CTTL
t_{CTp 2}
t_{CTp 2}
a 20
t_{CTp 2}
t_{CTp 2}
a 16
t_OEia
4-9 OE Signal
Inactive
After R E
CTTL
20
16
t_SEL0a
4-11 SEL0 Signal
Active (Note 3)
After R E
CTTL T1
50
36
t_SEL0ia
4-11 SEL0 Signal
Inactive
After R E
CTTL T4
24
22
t_SEL1a
4-11 SEL1 Signal
Active (Note 3)
After R E
CTTL T1
50
36
t_SEL1ia
4-11 SEL1 Signal
Inactive
After R E
CTTL T4
24
22
t_SEL3a
4-13 SEL3 Signal
Active
After R E
CTTL
20
18
t_SEL3ia
4-13 SEL3 Signal
Inactive
After R E
CTTL
24
22
t_RASa
4-9 RAS0–1 Signal
Active
After R E
CTTL
20
17
t_RASia
4-9 RAS0–1 Signal
Inactive
After R E
CTTL
20
17
t_RCa
4-9 CAS Signal
After F E
46
33
Active (Note 2)
RAS0– 1
t_RCLa
4-9 CAS Signal
After F E
50
40
Active (Notes 2 4) RAS0– 1
t_CASa
4-9 CAS Signal
Active
After R E
CTTL
20
16
t_CASia
4-9 CAS Signal
Inactive
After R E
CTTL
20
16
Note 1 Assuming WE0–1 load l CAS load
Note 2 Guaranteed by characterization Due to tester conditions these parameters are not 100% tested
Note 3 Generated asynchronous to CTTL as a function of the inputs AD0–15 A16–23 and ADS
Note 4 Assuming CAS load l RAS load
NS32FX200-25
Min
Max
32
Units
ns
0
ns
17
ns
t_{CTp 2} t_{CTp 2}
ns
a 17
45
ns
10
ns
t_{CTp 2} t_{CTp 2}
ns
a 16
16
ns
33
ns
20
ns
33
ns
20
ns
18
ns
20
ns
17
ns
17
ns
25
ns
30
ns
16
ns
16
ns
72