NS32FX100-15 Datasheet, PDF(24/94 Page) National Semiconductor (TI)

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NS32FX100-15 Datasheet, PDF (24/94 Pages) National Semiconductor (TI) – System Controller

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2 0 Architecture (Continued)

res

LSPP PDWP SNHP DISP

DISP Scanner Discharge Pulse Polarity

0 Active low

1 Active high

SNHP Sample and Hold Pulse Polarity

0 Active low

1 Active high

PDWP Peak Detector Window Polarity

0 Active low

1 Active high

LSPP Line Sync Pulse Polarity

0 Active low

1 Active high

SPP Scanner period pulse 8-bit register

7F Period pulse each 20 ms (TSLe255)

BF Period pulse each 10 ms (TSLe255 and 127)

DF Period pulse each 5 ms (TSLe255 63 127

and 191)

EF Period pulse each 2 5 ms (TSLe255 31 63

95 127 159 191 223)

SPP must be programmed with one of these four

values otherwise the period pulse frequency is un-

defined

(TSL indicates the appropriate TCU time slot )

SVHC Scanner Video handling Control Register

res BYPASS INVERT

VDILS

Video DAC Input Level Shift

Number of current steps to be added-to sub-

tracted-from the input of the Video DAC This

field is encoded as Sign bit a four magnitude

bits When the input of the video DAC is to be

incremented the sign bit bit 4 should be set to

ââ1ââ When it is to be decremented the sign bit

should be ââ0ââ Legal values for VDILS are in the

range

1F 10

0 0F

INVERT 0 Pixel not inverted by the pixel generator

1 Pixel inverted by the pixel generator

BYPASS (NS32FX200 only )

0 No bypass The comparator output is received

by the pixel genertor

1 Bypass enabled The SBYPS input is selected

by the pixel generator and the comparator output

is ignored

Note Only the NS32FX200 enables bypassing the video

comparator output through the SBYPS pin BYPASS

must always be cleared to ââ0ââ in the NS32FX100 and

NS32FV100

SVDB

Scanner Video DAC Buffer 16-bit register

Holds two bytes of compensation values The

lower byte is used first and the upper byte is used

for the next pixel

SBMS

SITSL

SMTSL

SDITH

Normally written by DMA channel 0

Accessible by software when the DMA channel is

either disabled or not allocated to the scanner

(i e MCFG EDMA0 e 0)

Scanner Bitmap Shifter Read Only 16-bit regis-

ter

Pixels are shifted from left to right i e the first

pixel in each word is the LSB

Scanner Interrupt Time Slot 8-bit register

Holds the number of the time-slot in which the

scanner interrupt pulse is generated

Scanner Motor Time Slot 8-bit register

Holds the number of the time-slot in which the

motor interrupt is generated

Note For an event to occur at the beginning of time slot n

the relevant register (SITSL or SMTSL) must be pro-

grammed with na1 If the written value equals the TSL

value (the current time slot) then the event will occur

either in the next time slot or after 257 time slots

Example If a scanner interrupt is to occur at the begin-

ning of time slot 255 the value ââ0ââ should be written

to SITSL

Scanner Dither Cyclic Buffer

accessible byte

res

The accessible byte is decoded into eight suc-

cessive address locations The eight dither val-

ues must be initialized before the video active

window is reached (the first write for the first pix-

el)

2 4 4 Usage Recommendations

1 Before activating the Scanner program the appropriate

Ports module registers PBDO PBMS PCDO PCMS

and PCEN to connect the Scanner module to the

NS32FX100 I O pins

2 To activate the Scanner Module set the ESCAN and

ECOUNT bits in the MCFG register

3 The number of current steps to be added to the input

of the Video DAC may be initialized by comparing the

Video DAC to the appropriate dither value and using an

iterative process to evaluate the required Input Level

Shift

4 The reference line may be initialized by software by

reading a white line and using an iterative process to

evaluate the best value of each pixelâs compensation

byte

5 When a scanner with an internal shading-compensation

circuit is used DMA channel 0 is free for external use

6 DMA channel 2 must be cleared before it can be used

this should be done through 32-bit dummy transactions

as follows

a activate DMA channel 2 for a 4-byte read transaction

b dummy write two words to ensure that at least two

bus cycles occur thus clearing the channel read SBMS

to clear the shifter counter

7 The SAVWD SLSD and SPDWD control registers

should be programmed by software to ignore the first

pixel after SPP

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