NS32FX100-15 Datasheet, PDF (30/94 Pages) National Semiconductor (TI) – System Controller

2 0 Architecture (Continued)
Memory-to-I O Operation
The data is first read from the source into the DMA Control-
ler and is subsequently written to the destination When the
DIR bit is ‘‘0’’ the first bus-cycle is used to read data from
the addressed device according to the ADCA counter while
the second bus-cycle is used to write the data into the im-
plied I O device according to the Implied I O Device
(ADRB) register When the DIR bit is ‘‘1’’ the first bus-cycle
is used to read data from the implied I O device using the
ADRB register while the second bus-cycle is used to write
the data into the addressed device according the ADCA
counter The number of bytes transferred in each cycle is
always one After the byte has been transferred the BLTC
counter is decremented by one The ADCA counter is incre-
mented or decremented by one or remains unchanged ac-
cording to the DEC and ADA bits in the MODE register
ADRB is not changed
Single Buffer Mode Operation
The block-transfer addresses and byte count should be first
written into the corresponding ADCA and BLTC counters
and the ADRB register The Operator Type (OT) bit in the
MODE register should be programmed for non auto-initialize
mode and the next Transfer Parameter Valid (VLD) bit in
the CNTL register should be cleared to ‘‘0’’ When the
Channel Enabled (CHEN) bit in the CNTL register is set to
‘‘1’’ the channel becomes active and responds to the trans-
fer requests When the BLTC counter reaches 0 the trans-
fer operation terminates The TC and Channel Overrun
(OVR) bits in the STAT register are set to ‘‘1’’ and Channel
Active (CHAC) is cleared to ‘‘0’’ If enabled through the ETC
bit a Terminal Count (TC) interrupt pulse is generated If the
EOVR bit in the STAT register is ‘‘1’’ the CHEN bit in the
CNTL register is forced to ‘‘0’’
Double Buffer Mode Operation
The operation is initiated by writing the block-transfer ad-
dress and byte count into the ADCA and BLTC counters and
ADRB register then programming the OT bit in the MODE
register for non auto-initialize mode When the CHEN bit in
the CNTL register is set to ‘‘1’’ the channel becomes active
and responds to transfer requests While the current block-
transfer is in progress the software can write the address
and byte count for the next block into the ADRA and BLTR
registers respectively and then set the VLD bit in the CNTL
register to ‘‘1’’ When the BLTC counter reaches 0 a TC
interrupt pulse is generated if enabled through the ETC bit
The TC bit is set to ‘‘1’’ and the DMA channel checks the
value of the VLD bit If it is ‘‘1’’ the channel copies ADRA
and BLTR values into ADCA and BLTC respectively clears
the VLD bit and starts the next block transfer If the VLD bit
is ‘‘0’’ the channel sets the OVR bit in the STAT register to
‘‘1’’ clears the CHAC bit and if the EOVR bit in the STAT
register is ‘‘1’’ it forces the CHEN bit to ‘‘0’’
Auto Initialize Mode Operation
The operation is initialized by writing the block address and
byte count values into the ADCA and BLTC counters and
into the ADRA ADRB and BLTR registers and program-
ming the OT bit in the MODE register for auto-initialize
mode When the CHEN bit in the CNTR register is set to
‘‘1’’ the channel becomes active and responds to DMA re-
quests When the BLTC counter reaches 0 a TC interrupt
pulse is generated if enabled through the ETC bit The TC
bit in the STAT register is set to ‘‘1’’ and the contents of the
ADRA and BLTR registers are copied to the ADCA and
BLTC counters respectively The operation is repeated
2 6 4 NS32FX200 DMA Channels
This section refers to the NS32FX200 since it has four DMA
channels while the NS32FX100 and NS32FV100 have only
three All references to channels 0 – 2 are applicable to all
chips All references to channel 3 are applicable to the
NS32FX200 only
Channel 0 is for the scanner reference line fetches (write to
SVDB)
Channel 1 is for the printer bitmap fetches
Channel 2 is for the scanner digitized-video writes
Channel 3 is for external use
Each of these three channels may be used as a general
purpose external DMA channel instead of the above men-
tioned use This is done by the MCFG register An external
DMA channel is accessible externally via the Ports module
Both MCFG bits and Port’s MS bits must be configured to
enable these DMA channels
All the channels include STAT ADCA BLTC MODE and
CNTL registers Channels 1 and 3 support double buffer
operations and include ADRA and BLTR registers Chan-
nels 0 – 2 support only Fly-By (Direct) DMA transactions
Channel 3 supports both Memory-to-I O and Fly-By DMA
transactions and therefore includes an ADRB register
Channel 0 has the highest priority followed by channel 1
channel 2 and with lowest priority channel 3 Refresh has
higher priority than DMA and it may occur between the two
bus transactions of a non fly-by DMA transaction Priority is
resolved when the bus is idle or on the last T3 of both CPU
and DMA transactions
2 6 5 Registers
A DMA channel contains a set of eight registers These reg-
isters are listed by their generic names The DMA channel
number should be added as a suffix to the register name
when referring to a specific channel register (e g ADCA0
ADCA1)
The registers ADCA BLTC STAT and MODE must be set
before activating the appropriate channel Undefined results
are obtained when these registers are written while the
channel is enabled Upon reset STAT and CNTL are cleared
to ‘‘0’’
MODE Mode Control register This register is used to
specify the channel operating mode
15
10 9 8
43
2
1
0
res
ADA
res
DIR NFBY DEC OT
OT Operation Type for channels 1 3 only (for chan-
nels 0 2 reserved)
0 Auto-Initialize mode disabled
1 Auto-Initialize mode enabled
30