NS32FX100-15 Datasheet, PDF (39/94 Pages) National Semiconductor (TI) – System Controller

2 0 Architecture (Continued)
Accessing MWSIO while the MWIRE is busy
(MWCSR BUSY e 1) may cause unpredictable
results
MWCSR MICROWIRE Control and Status register
7
5
4
3
1
0
res
CLKM
CDV
BUSY
BUSY
CDV
Read only Set to ‘‘1’’ during MWIRE transaction
Cleared to ‘‘0’’ on termination Used also as the
MICROWIRE interrupt source
Clock Divider
Divides the MCLK clock by 2 n where n e
0 5 to generate the MWIRE shift clock
CLKM
000 Non divided MCLK
001 MCLK 2
010 MCLK 4
011 MCLK 8
100 MCLK 16
101 MCLK 32
Other Reserved
Clocking mode
0 MWSO changed on MWSK rising edge
MWSK clock is high when MWIRE is idle
1 MWSO changed on MWSK falling edge
MWSK clock is low when MWIRE is idle
FIGURE 2-21 MICROWIRE Transaction (CLKM e 0)
TL EE 11331 – 26
FIGURE 2-22 MICROWIRE Transaction (CLKM e 1)
TL EE 11331 – 27
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