NS32FX100-15 Datasheet, PDF (52/94 Pages) National Semiconductor (TI) – System Controller

2 0 Architecture (Continued)
PORTS
PBDO
rw _l FE0812
7
6
5
4
3
DMAK3 ^SDIS DMAK1 ^SCLK2 STB3
DMAK2
DMAK0
2
STB2
1
STB1
0
STB0
15
12 11
10
9
8
res
SLS SCLK1 SPDW MWSK
PBMS
rw _l FE0814
15 12 11 10 9 8 7 6 5 4 3 2 1 0
res MS11 MS10 MS9 MS8 MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0
PBEN
15
rw _l FE0816
res
10
EN
PADI
7
PAMS
7
r _l FE0820
res
4
3
DMRQ3
2
MWSI
1
URXD
0
UTEN
rw _l FE0824
res
21
MS1
0
MS0
PCDI
7
UREN
r _l FE0830
6
5
4
3
2
SBPYS PCLK SNH
UTXD MWSO
DMRQ2 DMRQ1 DMRQ0
1
PIO1
0
PIO0
PCDO
7
UREN
rw _l FE0832
6
5
4
3
2
SBYPS PCLK SNH
UTXD MWSO
DMRQ DMRQ1 DMRQ0
1
PIO1
0
PIO0
PCMS
rw _l FE0834
7
6
5
4
3
2
1
0
MS7 MS6 MS5 MS4 MS3 MS2
res
PCEN
rw _l FE0838
7
6
5
4
3
2
1
0
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
PEXT
rw _l FE0840
15
0
PEXT
SMPH
rw _l FE0880
7
0
SMPH
PMPH
rw _l FE0883
7
0
PMPH
BMC
BMCFG
7
rw _l FE0910
res
321
0
DRA0
DPS
MWAIT
rw _l FE0912
15 14 12 11 10 8 7 6 4 3 2 0
WAITR WAIT3 IDLE2 WAIT2 IDLE1 WAIT1 IDLE0 WAIT0
Irregular behavior of some bit fields See detailed description of the rele-
vent module
52