NS32FX100-15 Datasheet, PDF (34/94 Pages) National Semiconductor (TI) – System Controller

2 0 Architecture (Continued)
FIGURE 2-17 DMA Memory to I O (Indirect) Read Transaction (DIR e 0 NFBY e 1)
TL EE 11331 – 22
The maximum throughput of a DMA channel is 3 125 Mbyte sec (One byte can be transferred at a rate of eight CTTL cycles per
transfer up to 25 MHz )
Note 1 Memory control signals (like CWAIT select and write enable) are generated according to the specifications of the accessed zone
Note 2 The NS32FX100 does not drive data onto AD0–15 till the end of T4 in memory
I O transactions (like NS32FX100 register read transactions)
v Note 3 A in the figure indicates DMA priority resolving points
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