NS32FX100-15 Datasheet, PDF (46/94 Pages) National Semiconductor (TI) – System Controller

2 0 Architecture (Continued)
Memory transactions are either adjacent (back-to-back) or
spaced with idle cycles To increase pre-charge time and to
avoid contention on the AD0–AD15 bus the memory trans-
actions may be spaced by idle cycles When an IDLEi field
of the Memory Wait-state Control (MWAIT) register is set
the NS32FX100 asserts the HOLD signal to force two idle
cycles (Figure 51)
2 11 2 1 Zones 0 1 (ROM and SRAM) Transactions
Zone 0 memories are selected by the SEL0 output pin
Zone 1 memories are selected by the SEL1 output pin Ex-
ternal logic may be used to sub-divide a zone into banks if
required In this case the external logic can add wait states
for a bank by manipulating the wait signal externally
A basic transaction starts in T1 when A16–A23 driven by
either the CPU or the NS32FX100 are valid Then MA1–
MA15 driven by the NS32FX100 are valid in T1 Either
SEL0 or SEL1 is asserted low by the NS32FX100 in T1
MA1 – MA15 hold address bits 1–15 The transaction may
be extended by wait states denoted by T3W The relevant
WAITi field of the MWAIT register controls the number of
T3W cycles On a read transaction OE is asserted low in T2
and de-asserted in T4 During a read transaction WE0 and
WE1 are inactive During a write transaction an even byte is
written when WE0 is asserted low an odd byte is written
when WE1 is asserted low and a word is written when both
WE0 and WE1 are asserted low The write-enable signal(s)
is asserted low in T2 and de-asserted in T3 (or last T3W if
the transaction is extended by wait states) During write
transactions OE is inactive
2 11 2 2 Zone 2 (Dynamic Memory) Transactions
(NS32FX200 and NS32FV100 only)
For the NS32FX100 Zone 2 is reserved
There are two non-interleaved memory banks in this zone
Access to the first bank is controlled by the RAS0 signal
Access to the second bank is controlled by the RAS1 signal
The size of the banks is configured by the DRAM Page Size
(DPS) field of the BMC Configuration Register (BMCFG)
(The terms DRAM ‘‘page size’’ and ‘‘column size’’ are inter-
changeable ) The second bank is adjacent to the first bank
Three basic DRAM cycles are supported read cycle early
write cycle and CAS before RAS refresh cycle During read
or early write transactions only one bank is selected ei-
ther RAS0 or RAS1 is active During refresh transactions
both RAS0 and RAS1 are active
The Timing Control Unit (TCU) issues refresh requests if
configured to do so by the TCU’s Refresh Enable register
(RFEN)
Arbitration between refresh transactions and CPU DMA
transactions If a refresh access is in progress the CPU or
DMA access will be postponed If a CPU or DMA access is
in progress the refresh will be postponed
If refresh is requested in T1 of CPU DMA access the re-
fresh will be served first On Zone 0 and Zone 1 access
SEL0 or SEL1 is active during T1 and T2 of the refresh (see
Figure 3-11 ) In any case neither OE nor WEi are active
during the refresh
The BMC module generates refresh transactions during
both Normal and Power Save modes but not during reset or
freeze mode However a refresh transaction already in
progress is completed even if reset or power-down is acti-
vated A freeze transaction is generated by the TCU module
during reset and freeze mode if configured to do so This
Freeze mode refresh transaction is also a CAS before RAS
transaction although its timing is different from that of the
normal refresh transaction The Freeze mode refresh trans-
action is described in the Timing Control Unit section
A basic DRAM transaction starts with row-address valid on
MA1 – MA11 in T1 Either RAS0 or RAS1 is asserted low in
T2 and the memory devices latch the row address then a
valid column address is driven onto MA1 – MA11 in T2 The
row and column address is multiplexed as follows
TABLE 2-4 DRAM Address Multiplexing
Multiplexed
Address
Row
Address
DPS e 00
Column Address
DPS e 01
DPS e 10
MA1
A1
A9
A10
A11
MA2
A2
A10
A11
A12
MA3
A3
A11
A12
A13
MA4
A4
A12
A13
A14
MA5
A5
A13
A14
A15
MA6
A6
A14
A15
A16
MA7
A7
A15
A16
A17
MA8
A8
A16
A17
A18
MA9
A9
A17
A18
A19
MA10
A10
A18
A19
A20
MA11
A11
A19
A20
A21
DPS DRAM Page Size control field in the BMCFG register
DPS e 11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
DPS
00
01
10
11
TABLE 2-5 DRAM Address Sizes
Banksize
128 kbyte
512 kbyte
2 Mbyte
8 Mbyte
Examples for DRAM Types
(64k x 4-bit) x 4 (64k x 4-bit) x 8
(256k x 4-bit) x 4 (256k x 4-bit) x 8
(1M x 4-bit) x 4 (64k x 4-bit) x 8
(4M x 4-bit) x 4
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