NS32FX100-15 Datasheet, PDF (63/94 Pages) National Semiconductor (TI) – System Controller

4 0 Device Specifications (Continued)
4 1 3 Output Signals
Signal
BUZCLK
CAS
CCLK
CWAIT
DMAK1
DMAK3
FOSCO
HOLD
INTR
MA1 – 15
MWSK
OE
PDO
PEXT
PMPH0 – 3
RAS0
RAS1
SCLK1
SCLK2 DMAK0
SCVO
SDFDBK
Pin Numbers
59
104
39
103
28
26
37
115
44
101 100 99
98 97 95
94 93 92
91 89 88
87 86 85
24
111
16
65
74 73 72
71
106
105
22
29
79
18
Description
Buzzer Clock Programmable frequency clock for the buzzer
DRAM Column Address Strobe Column address strobe for DRAM banks refresh
(NS32FX200 and NS32FV100 )
CPU Double Clock Feeds CPU’S OSCIN Asynchronous
Continuous Wait Low extends the memory cycle of the CPU
DMA Acknowledge Output for DMA channel 1 acknowledge or general purpose
output pin
DMA Acknowledge Output for DMA channel 3 acknowledge or general purpose
output pin
High-Speed Oscillator Out Asynchronous This line is used as the return path for
the crystal (if used)
Hold Request When low HOLD requests the bus from the CPU to perform DMA
operations or to insert idle bus cycles
Interrupt Request Low indicates that an interrupt request is being output to the CPU
Memory Address Bus Multiplexed DRAM address (NS32FX200 and NS32FV100 )
MICROWIRE Shift Clock Output or general purpose output pin
Output Enable Used by the addressed device to gate the data onto the data bus
Printer Bitmap Shifter Data Output from the bitmap shifter
External Expansion Port Latch Enable
Printer Motor Phases Four phase signals for driving the printer motor
DRAM Row Address Strobes Row address strobe for DRAM banks 0 and 1
(NS32FX200 and NS32FV100 )
Scanner Clock 1 Output pixel clock or general purpose output pin
Scanner Clock 2 Output pixel clock or DMA Acknowledge output for DMA channel
0 acknowledge or general purpose output pin
Scanner Compensated Video Out Analog current for use by ABC or optional video
enhancement circuit
Sigma-Delta Feedback Feedback input to the SDC analog receiver Asynchronous
output signal
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