NS32FX100-15 Datasheet, PDF (70/94 Pages) National Semiconductor (TI) – System Controller

4 0 Device Specifications (Continued)
4 6 SWITCHING CHARACTERISTICS
4 6 1 Definitions
All the timing specifications given in this section refer to
0 8V or 2 0V on the rising or falling edges of all the signals
as illustrated in the following Figures 4-3 to 4-5 unless spe-
cifically stated otherwise The capacitive load is assumed to
be 20 pF on the CCLK and 50 pF on all the other output
signals
Abbreviations
L E Leading Edge
T E Trailing Edge
R E Rising Edge
F E Falling Edge
TL EE 11331–55
FIGURE 4-3 TTL Output Signals
Specification Standard
Abbreviations
Reference to Signal
L E Leading Edge
T E Trailing Edge
Reference to Clock
R E Rising Edge
F E Falling Edge
TL EE 11331 – 56
FIGURE 4-4 TTL Input Signals Specification Standard
TL EE 11331–57
FIGURE 4-5 CMOS Output Signals
Specification Standard
TL EE 11331 – 58
FIGURE 4-6 CMOS Input Signals
Specification Standard
FIGURE 4-7 Input Hysteresis
TL EE 11331 – 59
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