MC68HC908GZ8 Datasheet, PDF (96/344 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
NOTE:
these bits. (See 7.3.3 PLL Circuits, 7.3.6 Programming the PLL, and 7.5.5
PLL VCO Range Select Register.)
Table 7-4. VPR1 and VPR0 Programming
VPR1 and VPR0
E
00
0
01
1
10
2⁽¹⁾
1. Do not program E to a value of 3.
VCO Power-of-Two
Range Multiplier
1
2
4
Verify that the value of the VPR1 and VPR0 bits in the PCTL register are
appropriate for the given reference and VCO clock frequencies before enabling the
PLL. See 7.3.6 Programming the PLL for detailed instructions on selecting the
proper value for these control bits.
7.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
• Selects automatic or manual (software-controlled) bandwidth control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking mode
Address: $0037
Bit 7
6
5
4
3
2
1
Bit 0
Read:
LOCK
0
0
0
0
AUTO
ACQ
R
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 7-5. PLL Bandwidth Control Register (PBWC)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control. When
initializing the PLL for manual operation (AUTO = 0), clear the ACQ bit before
turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set when the
VCO clock, CGMVCLK, is locked (running at the programmed frequency).
Data Sheet
96
Clock Generator Module (CGM)
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MC68HC908GZ8
MOTOROLA