MC68HC908GZ8 Datasheet, PDF (197/344 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
MSCAN08 Controller (MSCAN08)
Programmer’s Model of Control Registers
16.13.13 MSCAN08 Identifier Mask Registers (CIDMR0–CIDMR3)
The identifier mask registers specify which of the corresponding bits in the identifier
acceptance register are relevant for acceptance filtering. For standard identifiers it
is required to program the last three bits (AM2–AM0) in the mask register CIDMR1
to ‘don’t care’.
CIDMRO Address: $0514
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Reset:
Unaffected by reset
CIDMR1 Address: $0515
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Reset:
Unaffected by reset
CIDMR2 Address: $0516
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Reset:
Unaffected by reset
CIDMR3 Address: $0517
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Reset:
Unaffected by reset
Figure 16-27. Identifier Mask Registers
(CIDMR0–CIDMR3)
NOTE:
AM7–AM0 — Acceptance Mask Bits
If a particular bit in this register is cleared, this indicates that the corresponding
bit in the identifier acceptance register must be the same as its identifier bit
before a match will be detected. The message will be accepted if all such bits
match. If a bit is set, it indicates that the state of the corresponding bit in the
identifier acceptance register will not affect whether or not the message is
accepted.
1 = Ignore corresponding acceptance code register bit.
0 = Match corresponding acceptance code register and identifier bits.
The CIDMR0–CIDMR3 registers can be written only if the SFTRES bit in the
CMCR0 is set
MC68HC908GZ8
MOTOROLA
MSCAN08 Controller (MSCAN08)
For More Information On This Product,
Go to: www.freescale.com
Data Sheet
197