MC68HC908GZ8 Datasheet, PDF (50/344 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Resets and Interrupts
All internal reset sources pull the RST pin low for 32 CGMXCLK cycles to allow
resetting of external devices. The MCU is held in reset for an additional 32
CGMXCLK cycles after releasing the RST pin.
4.2.3.1 Power-On Reset (POR)
A power-on reset (POR) is an internal reset caused by a positive transition on the
V_DD pin. V_DD at the POR must below V_POR to reset the MCU. This distinguishes
between a reset and a POR. The POR is not a brown-out detector, low-voltage
detector, or glitch detector.
A power-on reset:
• Holds the clocks to the central processor unit (CPU) and modules inactive
for an oscillator stabilization delay of 4096 CGMXCLK cycles
• Drives the RST pin low during the oscillator stabilization delay
• Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization
delay
• Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles
after the oscillator stabilization delay
• Sets the POR and LVI bits in the SIM reset status register and clears all
other bits in the register
OSC1
PORRST⁽¹⁾
CGMXCLK
CGMOUT
RST PIN
4096
32
CYCLES CYCLES
1. PORRST is an internally generated power-on reset pulse.
Figure 4-1. Power-On Reset Recovery
4.2.3.2 Computer Operating Properly (COP) Reset
A computer operating properly (COP) reset is an internal reset caused by an
overflow of the COP counter. A COP reset sets the COP bit in the SIM reset status
register.
To clear the COP counter and prevent a COP reset, write any value to the COP
control register at location $FFFF.
Data Sheet
50
Resets and Interrupts
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MC68HC908GZ8
MOTOROLA