MC68HC908GZ8 Datasheet, PDF (320/344 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timer Interface Module (TIM)
Table 23-3. Mode, Edge, and Level Selection
MSxB:MSxA
X0
X1
00
00
00
01
01
01
1X
1X
1X
ELSxB:ELSxA
00
00
01
10
11
01
10
11
01
10
11
Mode
Configuration
Output
preset
Pin under port control;
initial output level high
Pin under port control;
initial output level low
Capture on rising edge only
Input
capture
Capture on falling edge only
Capture on rising or
falling edge
Output compare
or PWM
Toggle output on compare
Clear output on compare
Set output on compare
Buffered output
compare
or buffered
PWM
Toggle output on compare
Clear output on compare
Set output on compare
NOTE:
NOTE:
Before enabling a TIM channel register for input capture operation, make sure that
the PTD/TCHx pin is stable for at least two bus clocks.
TOVx — Toggle On Overflow Bit
When channel x is an output compare channel, this read/write bit controls the
behavior of the channel x output when the TIM counter overflows. When
channel x is an input capture channel, TOVx has no effect.
Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
When TOVx is set, a TIM counter overflow takes precedence over a channel x
output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of
buffered and unbuffered PWM signals to 100%. As Figure 23-11 shows, the
CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays
at the 100% duty cycle level until the cycle after CHxMAX is cleared.
Data Sheet
320
Timer Interface Module (TIM)
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MC68HC908GZ8
MOTOROLA