MC68HC908GZ8 Datasheet, PDF (287/344 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI) Module
Interrupts
NOTE:
NOTE:
of the eighth data bit. When CPHA = 1, the transmission begins when the SPSCK
leaves its idle level and SS is already low. The transmission continues until the
SPSCK returns to its idle level following the shift of the last data bit. See 21.5
Transmission Formats.
Setting the MODF flag does not clear the SPMSTR bit. The SPMSTR bit has no
function when SPE = 0. Reading SPMSTR when MODF = 1 shows the difference
between a MODF occurring when the SPI is a master and when it is a slave.
When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0) and later
unselected (SS is at logic 1) even if no SPSCK is sent to that slave. This happens
because SS at logic 0 indicates the start of the transmission (MISO driven out with
the value of MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and
then later unselected with no transmission occurring. Therefore, MODF does not
occur since a transmission was never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU
interrupt request if the ERRIE bit is set. The MODF bit does not clear the SPE bit
or reset the SPI in any way. Software can abort the SPI transmission by clearing
the SPE bit of the slave.
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK clocks, even if it
was already in the middle of a transmission.
To clear the MODF flag, read the SPSCR with the MODF bit set and then write to
the SPCR register. This entire clearing mechanism must occur with no MODF
condition existing or else the flag is not cleared.
21.8 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests. See
Table 21-2.
Table 21-2. SPI Interrupts
Flag
SPTE
Transmitter empty
SPRF
Receiver full
OVRF
Overflow
MODF
Mode fault
Request
SPI transmitter CPU interrupt request
(DMAS = 0, SPTIE = 1, SPE = 1)
SPI receiver CPU interrupt request
(DMAS = 0, SPRIE = 1)
SPI receiver/error interrupt request
(ERRIE = 1)
SPI receiver/error interrupt request
(ERRIE = 1)
Reading the SPI status and control register with SPRF set and then reading the
receive data register clears SPRF. The clearing mechanism for the SPTE flag is
always just a write to the transmit data register.
MC68HC908GZ8
MOTOROLA
Serial Peripheral Interface (SPI) Module
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Data Sheet
287