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MC68HC908GZ8 Datasheet, PDF (34/344 Pages) Motorola, Inc – Microcontrollers
Memory Map
Freescale Semiconductor, Inc.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
ESCI Status Register 2 Read:
BKF
RPF
$0017
(SCS2) Write:
See page 243. Reset:
0
0
0
0
0
0
0
0
$0018
ESCI Data Register Read: R7
R6
R5
R4
R3
R2
R1
R0
(SCDR) Write: T7
T6
T5
T4
T3
T2
T1
T0
See page 244. Reset:
Unaffected by reset
ESCI Baud Rate Register Read: LINT
LINR
SCP1
SCP0
R
SCR2
SCR1
SCR0
$0019
(SCBR) Write:
See page 244. Reset:
0
0
0
0
0
0
0
0
$001A
$001B
$001C
$001D
$001E
Keyboard Status Read:
and Control Register Write:
(INTKBSCR)
See page 143. Reset:
Keyboard Interrupt Enable Read:
Register (INTKBIER) Write:
See page 144. Reset:
Timebase Module Control Read:
Register (TBCR) Write:
See page 302. Reset:
IRQ Status and Control Read:
Register (INTSCR) Write:
See page 138. Reset:
Configuration Register 2 Read:
(CONFIG2)(1) Write:
See page 104.
Reset:
0
0
KBIE7
0
TBIF
0
0
0
0
0
0
0
KBIE6
0
TBR2
0
0
0
0
0
0
0
KBIE5
0
TBR1
0
0
0
0
0
0
KEYF
0
IMASKK MODEK
ACKK
0
0
0
0
0
KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
0
TBR0
0
0
0
0
0
0
0
TACK
0
IRQF1
0
0
TBIE
0
0
ACK1
0
0
0
TBON
R
0
0
IMASK1 MODE1
0
0
MSCAN-E
N
TMCLKSEL
OSCENIN-
STOP
SCIBDSRC
0
0
0
1
$001F
Configuration Register 1 Read:
(CONFIG1)(1) Write:
See page 104. Reset:
COPRS
0
LVISTOP
0
LVIRSTD
0
LVIPWRD
0
LVI5OR3
(Note 1)
0
SSREC
0
STOP
0
COPD
0
1. One-time writable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).
Timer 1 Status and Control Read: TOF
TOIE TSTOP
0
0
$0020
Register (T1SC) Write: 0
TRST
See page 315. Reset:
0
0
1
0
0
Timer 1 Counter Read: Bit 15
14
13
12
11
$0021 Register High (T1CNTH) Write:
See page 317. Reset:
0
0
0
0
0
PS2
PS1
PS0
0
0
0
10
9
Bit 8
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 8)
Data Sheet
34
Memory Map
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MC68HC908GZ8
MOTOROLA